Semiconductor memory device incorporating redundancy memory cells having parallel test function

Claim 1

A semiconductor memory device comprising: a plurality of memory blocks each incorporating a plurality of memory cells and a plurality of redundancy memory cells; said memory blocks being divided into a plurality of test groups; said memory cells being located at intersections between a plurality of word lines and a plurality of bit lines; said redundancy memory cells being located at intersections between a plurality of redundancy word lines and said bit lines; normal decoder means for accessing one of said memory cells by a first address having a first address space; said normal decoder means being separately provided for each of said memory blocks, comprising: a plurality of series of normal word decoders incorporating drivers, each series provided for one of said memory blocks, for activating one of said word lines thereof; a parallel test means for simultaneously testing a predetermined number of said memory cells by a degenerate address showing degeneracies of predetermined values of said first address; redundancy decoder means for accessing said redundancy memory cells by a second address having a second address space; said redundancy decoder means being commonly provided for each of said test groups, comprising: a plurality of redundancy driving circuits each provided for one of said memory blocks, for activating one of said redundancy word lines thereof; and a single redundancy word decoder, provided commonly for all of said test groups, for activating said redundancy driving circuits thereof; and said degenerate address having a degenerate address space being written as said second address into only one location of said redundancy decoder means to replace at least one defective memory cell with its corresponding redundancy memory cell when at least one of said predetermined number of said memory cells tested by said degenerate address is determined to be defective.