MOSFET device having depletion layer

Claim 2

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; and third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the source region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 3

The semiconductor device of claim 1, wherein the third regions have an impurity concentration higher than an impurity concentration in the second region.

Claim 4

The semiconductor device of claim 1, wherein the substrate has an impurity concentration lower than an impurity concentration in the third regions, and a depletion layer caused by the drain region reaches the substrate.

Claim 5

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; a fourth region formed by the substrate; and fifth regions provided on the substrate and having the second conduction type, the fifth regions having an impurity concentration lower than an impurity concentration in the source region and the drain region, wherein a first one of the fifth regions extends between the fourth region and the source region, and a second one of the fifth regions extends between the fourth region and the drain region; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the drain region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 6

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; a fourth region formed by the substrate; and fifth regions provided on the substrate and having the second conduction type, the fifth regions having an impurity concentration lower than an impurity concentration in the source region and the drain region, wherein a first one of the fifth regions extends between the fourth region and the source region, and a second one of the fifth regions extends between the fourth region and the drain region; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the drain region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 7

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; and a fourth region formed by the substrate and connecting with the second region via a pn junction; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, wherein the second region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused in the second region by the pn junction with the first region and a depth-direction width of a depletion layer caused by the pn junction with the fourth region, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width depletion layer caused by the source region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 8

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; and a fourth region formed by the substrate and connecting with the second region via a pn junction; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, wherein the second region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused in the second region by the pn junction with the first region and a depth-direction width of a depletion layer caused by the pn junction with the fourth region, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width depletion layer caused by the source region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 9

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; and LDD regions provided on the substrate and having the second conduction type, the LDD regions having an impurity concentration lower than an impurity concentration in the source region and the drain region, wherein a first one of the LDD regions extends between the first region and the source region, and a second one of the LDD regions extends between the first region and the drain region; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the drain region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 10

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; and LDD regions provided on the substrate and having the second conduction type, the LDD regions having an impurity concentration lower than an impurity concentration in the source region and the drain region, wherein a first one of the LDD regions extends between the first region and the source region, and a second one of the LDD regions extends between the first region and the drain region; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the drain region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 11

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; a second insulating film provided on the substrate and surrounding an area containing the gate insulating film, the gate electrode, the source region, the drain region, the first region, the second region, and the third regions to provide an isolation from a neighboring device; and a fourth region provided on the substrate and extending between the first region and the second insulating film, the fourth region having a conductivity higher than a conductivity of the first region; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the drain region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Claim 12

A semiconductor device comprising: a substrate having a first conduction type; a gate insulating film provided on the substrate; a gate electrode formed on the gate insulating film; a source region provided on the substrate and having a second conduction type different from the first conduction type; a drain region provided on the substrate and having the second conduction type; wherein the source region and the drain region extend below the gate insulating film and are located at respective sides of the gate electrode; a first region provided on the substrate and having the first conduction type, the first region extending below the gate insulating film; a second region provided on the substrate and having the second conduction type, the second region extending below the first region and being separated from the gate insulating film by the first region, the second region connecting with the first region via a pn junction; third regions provided on the substrate and having the first conduction type, the third regions connecting with the second region via respective pn junctions, wherein a first one of the third regions extends between the second region and the source region and separates the second region from the source region, and a second one of the third regions extends between the second region and the drain region and separates the second region from the drain region; a second insulating film provided on the substrate and surrounding an area containing the gate insulating film, the gate electrode, the source region, the drain region, the first region, the second region, and the third regions to provide an isolation from a neighboring device; and a fourth region provided on the substrate and extending between the first region and the second insulating film, the fourth region having a conductivity higher than a conductivity of the first region; wherein the first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode, and wherein the third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the drain region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.