Input/output checker for a memory array

Claim 2

Apparatus for receiving data from any of a plurality of data sources and having capability for testing data input and output circuitry, and having the capability of retrievably storing data in an EPROM and for outputting data to any of a plurality of output devices, the input circuitry being circuitry for providing data from at least one of said plurality of data sources to said EPROM for writing data in said EPROM, the output circuitry for providing data read from the EPROM to at least one of said plurality of output devices, said EPROM having a plurality of normally-used, selectable and deselectable memory elements organized in rows and columns, said input and output circuitry including circuitry for receiving first data from at least one of said plurality of data sources and for outputting second data, in response to input of said first data, the apparatus comprising: first means for deselecting all rows of said normally-used memory elements in said EPROM; testing means, coupled to said input and output circuitry for receiving said second data; second means, in said testing means, for outputting said second data on at least a first bitline, without writing said second data to said EPROM and without reading any of said memory elements; third means for evaluating the data on said bitline without reading any of said memory elements to permit comparing said evaluated data to said first data to check for desired functioning of said input and output circuitry.

Claim 3

Apparatus, as claimed in claim 1, wherein said second data is identical to said first data.

Claim 4

In a circuit which includes an erasable programmable read only memory, said memory including a plurality of memory elements arranged in a plurality of rows and columns, elements in each row connected to a row line, elements in each column connected to a column line, a row decoder coupled to each of said rows for controllably selecting at least one row by placing a predetermined voltage on said row line, a column decoder coupled to each of said columns for controllably selecting at least one column by connecting a column line to a bitline, at least a first of said plurality of memory elements being programmable in response to receiving data-dependent predetermined voltage when the corresponding column line and row line are both selected, said circuit also including input-output circuitry, including first circuitry for receiving data to be written to said memory for programming of said memory and second circuitry for supplying said data to said bitline, apparatus including a device for testing said input-output circuitry without writing data to said memory, the apparatus comprising: a plurality of logic gates, coupled to said first circuitry, and configured to receive said data from said first circuitry and coupled to receive a test signal, and having an output coupled to said bitline to output said data to said bitline for writing when said test signal is in a first binary state and to disable reading and writing of said plurality of memory elements and to control a third circuit when said test signal is in a second binary state, said third circuit being configured to connect said bitline to a ground voltage level only when said data is in a first binary state, without reading any of said plurality of memory elements; and circuitry, coupled to said bitline, for evaluating whether said bitline has been coupled to a ground voltage without reading any of said plurality of memory elements.

Claim 5

In a circuit which includes an erasable programmable read only memory, said memory including a plurality of memory elements arranged in a plurality of rows and columns, elements in each row connected to a row line, elements in each column connected to a column line, a row decoder coupled to each of said rows for controllably selecting at least one row by placing a predetermined voltage on said row line, a column decoder coupled to each of said columns for controllably selecting at least one column by connecting a column line to a bitline, at least a first of said plurality of memory elements being programmable in response to receiving data-dependent predetermined voltage when the corresponding column line and row line are both selected, said circuit also including input-output circuitry, including first circuitry for receiving data to be written to said memory for programming of said memory and second circuitry for supplying said data to said bitline, apparatus including a device for testing said input-output circuitry without writing data to said memory, the apparatus comprising: a plurality of logic gates, coupled to said first circuitry, and configured to receive said data from said first circuitry and coupled to receive a test signal, and having an output coupled to said bitline to output said data to said bitline for writing when said test signal is in a first binary state and to disable reading and writing of said plurality of memory elements and to control a third circuit when said test signal is in a second binary state, said third circuit being configured to connect said bitline to a ground voltage level only when said data is in a first binary state, without reading any of said plurality of memory elements; and circuitry, coupled to said bitline, for evaluating whether said bitline has been coupled to a ground voltage without reading any of said plurality of memory elements.

Claim 8

A method, as claimed in claim 4, wherein said EPROM includes a plurality of selectable rows and wherein said step of deselecting includes deselecting all rows of said EPROM.

Claim 9

A method, as claimed in claim 4, wherein said EPROM includes a sense amp that operates to evaluate data stored in said EPROM and wherein said step of evaluating includes using said sense amp to evaluate said second data.

Claim 10

A method, as claimed in claim 4, further comprising the step of: repeating the testing of said input-output devices by repeating steps a) through f), without first erasing data stored in said EPROM.

Claim 13

Apparatus as claimed in claim 8 wherein said second circuitry comprises at least one sense amp.

Claim 14

Apparatus as claimed in claim 9 wherein said sense amp is coupled to said memory for evaluating data stored in said memory.

Claim 15

Apparatus as claimed in claim 8 wherein said memory is erasable programmable read only memory.

Claim 16

Apparatus as claimed in claim 11 wherein said memory is one time programmable erasable programmable read only memory.

Claim 17

Apparatus as claimed in claim 11 wherein said apparatus includes a microcontroller.

Claim 18

Apparatus as claimed in claim 8 wherein said data includes at least one bit which can be in one of two data-signal binary states and further comprising a third circuitry for coupling said bitline to ground voltage only when said data bit is in said first data-signal binary state and said test-signal is asserted.