US5459354A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with improved insulation of wiring structure from a gate electrode
Assignee: United Microelectronics Corp
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Filing: 1993-12-20
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Granted: 1995-10-17
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Expires: 2013-12-20
Abstract
Abstract A semiconductor device comprises a silicon substrate, a gate electrode including a conductive layer formed on the silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering the conductive layer, a conductive region formed in the surface of the silicon substrate at its portion adjacent to the gate electrode, a second insulating layer formed so as to cover the gate electrode and the silicon substrate, a third insulating layer formed so as to cover the second insulating layer, a contact hole formed by etching to penetrate the third and second insulating layers and to reach the conductive region, and a wiring layer formed to cover the third insulating layer and having a contact part extending inside the contact hole, and electrically connect to the conductive region, the second insulating layer being made of a material having a selected ratio of an etching rate relative to an etching rate of a material of the first insulating layer in formation of the contact hole by etching, and sections of the third and second insulating layers exposed to an inner side of the contact hole being flush along the inner side.
Inventors
- 👤 Tatsuya Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:29
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
204 words
A wiring structure in a semiconductor device comprising: a silicon substrate; a gate electrode including a conductive layer formed on said silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering said conductive layer; a conductive region formed in the surface of said silicon substrate at its portion adjacent to said gate electrode; a second insulating layer formed so as to cover said gate electrode and said silicon substrate; a third insulating layer formed to cover said second insulating layer; a contact hole formed by etching to penetrate said third and second insulating layers and to reach said conductive region; and a wiring layer formed to cover said third insulating layer and having a contact part extending inside said contact hole, and electrically connected to said conductive region, wherein said second insulating layer is made of a material having a selected ratio of an etching rate relative to an etching rate of a material of said first insulating layer in formation of said contact hole by etching and wherein sections of said third and second insulating layers exposed to an inner side of the contact hole are flush along said inner side.
Claim 2
Dependent Claim
204 words
A wiring structure in a semiconductor device comprising: a silicon substrate; a gate electrode including a conductive layer formed on said silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering said conductive layer; a conductive region formed in the surface of said silicon substrate at its portion adjacent to said gate electrode; a second insulating layer formed so as to cover said gate electrode and said silicon substrate; a third insulating layer formed to cover said second insulating layer; a contact hole formed by etching to penetrate said third and second insulating layers and to reach said conductive region; and a wiring layer formed to cover said third insulating layer and having a contact part extending inside said contact hole, and electrically connected to said conductive region, wherein said second insulating layer is made of a material having a selected ratio of an etching rate relative to an etching rate of a material of said first insulating layer in formation of said contact hole by etching and wherein sections of said third and second insulating layers exposed to an inner side of the contact hole are flush along said inner side.
Claim 3
Dependent Claim
35 words
A wiring structure as claimed in claim 1, wherein said first insulating layer includes an insulating layer formed on said conductive layer and a side wall formed on a side surface of said conductive layer.
Claim 4
Dependent Claim
37 words
A wiring structure as claimed in claim 1, wherein the etching rate of the second insulating film is higher than the etching rate of the first insulating film in the etching for formation of said contact hole.
Claim 5
Dependent Claim
55 words
A wiring structure as claimed in claim 1, wherein said second insulating layer is made of a material so as to make a ratio of an etching rate of said second insulating layer relative to an etching rate of said first insulating material at the etching in formation of said contact hole higher than 1.5.
Claim 6
Dependent Claim
28 words
A wiring structure as claimed in claim 1, wherein said first insulating film is a silicon dioxide film, and said second insulating film is a silicon nitride film.
Claim 7
Dependent Claim
225 words
A wiring structure in a semiconductor device comprising: a silicon substrate; a gate electrode including a conductive layer formed on said silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering said conductive layer; a conductive region formed in the surface of said silicon substrate at its portion adjacent to said gate electrode; a second insulating layer formed so as to cover said gate electrode and said silicon substrate; a third insulating layer formed so as to cover said second insulating layer; a contact hole formed by etching to extend through said third and second insulating layers and to reach said conductive region; and a wiring layer formed to cover said third insulating layer, extend inside said contact hole, and electrically connect to said conductive region, wherein said second insulating layer is made of a material having a ratio of an etching rate selected relative to an etching rate of a material of said first insulating layer such that in formation of said contact hole by etching said first insulating layer is prevented from being removed by etching while said second insulating layer is completely removed at the bottom portion of said contact hole and wherein said second and third insulating layers have their portions facing said contact hole aligned with each other.
Claim 8
Dependent Claim
225 words
A wiring structure in a semiconductor device comprising: a silicon substrate; a gate electrode including a conductive layer formed on said silicon substrate with a gate insulating film disposed between the conductive layer and the silicon substrate and a first insulating layer covering said conductive layer; a conductive region formed in the surface of said silicon substrate at its portion adjacent to said gate electrode; a second insulating layer formed so as to cover said gate electrode and said silicon substrate; a third insulating layer formed so as to cover said second insulating layer; a contact hole formed by etching to extend through said third and second insulating layers and to reach said conductive region; and a wiring layer formed to cover said third insulating layer, extend inside said contact hole, and electrically connect to said conductive region, wherein said second insulating layer is made of a material having a ratio of an etching rate selected relative to an etching rate of a material of said first insulating layer such that in formation of said contact hole by etching said first insulating layer is prevented from being removed by etching while said second insulating layer is completely removed at the bottom portion of said contact hole and wherein said second and third insulating layers have their portions facing said contact hole aligned with each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-16 | 1999-04-17 | 1999-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-16 | 2003-04-17 | 2003-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-16 | 2007-04-17 | 2007-10-17 | $7700.00 | Window Closed / Lapsed |