Pseudo-exhaustive self-test technique

Claim 1

A method for pseudo-exhaustively testing a digital integrated circuit in which the combinational elements have been partitioned into sub-cones, each sub-cone having a single output and no more than a user-selected number (w) of inputs, each input having been pre-assigned to receive a particular one of a set of test vectors, the method comprising the steps of: exiting normal operations and entering a test mode; generating a set of w test vectors by the steps of: generating a binary counting sequence of w vectors, a 1 , a 2 . . . a w , each vector being 2 w bits in length; generating a second sequence of w vectors b 1 , b 2 . . . b w , each generated in accordance with the relationship b.sub.i =(⊕.sub.i=1,w a.sub.i)⊕a.sub.i where b i represents a successive one of the second vectors and a i represents a successive one of the vectors in the binary counting sequence; grouping the vectors a 1 , a 2 . . . a w and b 1 , b 2 . . . b w into subsets such that each subset satisfies at least one of the following conditions: (1) the subset has a single pair of i elements (a i b i ), (2) the subset has w elements but contains no i pairs and the number of b i 's is even, or (3) the subset has less than w elements and no i pairs; applying a separate vector of each subset of the generated test vectors to a pre-assigned input of a respective sub-cone to exhaustively test the sub-cone, each test vector of the subset, when applied to the correspondingly assigned input of the sub-cone, causing the sub-cone to generate a response in accordance with the applied test vector; successively compacting the responses produced by the sub-cones to yield a signature indicative of the operation of the circuit; and comparing the signature to a predetermined signature to establish whether the circuit is fault-free.

Claim 2

A method for pseudo-exhaustively testing a digital integrated circuit in which the combinational elements have been partitioned into sub-cones, each sub-cone having a single output and no more than a user-selected number (w) of inputs, each input having been pre-assigned to receive a particular one of a set of test vectors, the method comprising the steps of: exiting normal operations and entering a test mode; generating a set of w test vectors by the steps of: generating a binary counting sequence of w vectors, a 1 , a 2 . . . a w , each vector being 2 w bits in length; generating a second sequence of w vectors b 1 , b 2 . . . b w , each generated in accordance with the relationship b.sub.i =(⊕.sub.i=1,w a.sub.i)⊕a.sub.i where b i represents a successive one of the second vectors and a i represents a successive one of the vectors in the binary counting sequence; grouping the vectors a 1 , a 2 . . . a w and b 1 , b 2 . . . b w into subsets such that each subset satisfies at least one of the following conditions: (1) the subset has a single pair of i elements (a i b i ), (2) the subset has w elements but contains no i pairs and the number of b i 's is even, or (3) the subset has less than w elements and no i pairs; applying a separate vector of each subset of the generated test vectors to a pre-assigned input of a respective sub-cone to exhaustively test the sub-cone, each test vector of the subset, when applied to the correspondingly assigned input of the sub-cone, causing the sub-cone to generate a response in accordance with the applied test vector; successively compacting the responses produced by the sub-cones to yield a signature indicative of the operation of the circuit; and comparing the signature to a predetermined signature to establish whether the circuit is fault-free.