Patent US5457649A successfully refreshed from Google Patents.
US5457649A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method therefor
Assignee: Microchip Technology Inc
•
Filing: 1994-08-26
•
Granted: 1995-10-10
•
Expires: 2014-08-26
Abstract
Abstract A semiconductor device used as a semiconductor memory device is disclosed which is made of an amorphous silicon material that provides either a "1" or "0" memory state when the amorphous silicon material is in a non-conduction or insulating state and a "0" or "1" memory state when the amorphous silicon material is transformed, by use of a breakdown voltage applied to electrodes coupled thereto, into a conducting state. The amorphous silicon material is located adjacent to a doped semiconductor region of a semiconductor substrate separated only by a relatively thin primarily metal ohmic contact. The resulting semiconductor structure for the semiconductor device or semiconductor memory device is primarily a single level metalization type structure. A write-once, read-only semiconductor memory array is also disclosed which uses, as each memory cell of the array, one of the disclosed semiconductor memory devices. Methods for producing the semiconductor memory device and write-once, read-only semiconductor memory array are also disclosed.
Inventors
- 👤 Eric C. Eichman
- 👤 Thomas C. Salt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:48
CPC Classifications
G; G11; G11C; G11C13/00; G11C13/0002; G11C13/0004; G11C17/00; G11C17/14; G11C17/16; H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10W20/40; H10W20/49; H10W20/493; G11C2213/00; G11C2213/30; G11C2213/33
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
199 words
A semiconductor memory device comprising, in combination: a semiconductor substrate having a doped semiconductor region and a dielectric layer on one surface thereof and at least one opening located in said dielectric layer to permit electrical contact to be made to said doped semiconductor region; a primarily metal ohmic contact located in said opening and in electrical ohmic contact with said doped semiconductor region of said semiconductor substrate; semiconductor memory means in contact with said ohmic contact and comprising a-silicon material for providing a non-conducting state of memory representative of one of a "1" and "0" memory state when said a-silicon material functions as an insulator and for providing a conducting state of memory representative of the other of said "1" and "0" memory state when said a-silicon material functions as an electrical conductor; and electrode means including said ohmic contact and said doped semiconductor region as at least one electrode coupled to said semiconductor memory means for selectively applying thereto one of a voltage below a preselected breakdown voltage to maintain said a-silicon material in said non-conducting state and a voltage at least equal to said preselected breakdown voltage to place said a-silicon material in said conducting state.
Claim 2
Dependent Claim
199 words
A semiconductor memory device comprising, in combination: a semiconductor substrate having a doped semiconductor region and a dielectric layer on one surface thereof and at least one opening located in said dielectric layer to permit electrical contact to be made to said doped semiconductor region; a primarily metal ohmic contact located in said opening and in electrical ohmic contact with said doped semiconductor region of said semiconductor substrate; semiconductor memory means in contact with said ohmic contact and comprising a-silicon material for providing a non-conducting state of memory representative of one of a "1" and "0" memory state when said a-silicon material functions as an insulator and for providing a conducting state of memory representative of the other of said "1" and "0" memory state when said a-silicon material functions as an electrical conductor; and electrode means including said ohmic contact and said doped semiconductor region as at least one electrode coupled to said semiconductor memory means for selectively applying thereto one of a voltage below a preselected breakdown voltage to maintain said a-silicon material in said non-conducting state and a voltage at least equal to said preselected breakdown voltage to place said a-silicon material in said conducting state.
Claim 3
Dependent Claim
29 words
The semiconductor memory device of claim 1 wherein said non-conducting state of memory is said "1" memory state and said conducting state of memory is said "0" memory state.
Claim 4
Dependent Claim
29 words
The semiconductor memory device of claim 1 wherein said non-conducting state of memory is said "0" memory state and said conducting state of memory is said "1" memory state.
Claim 5
Dependent Claim
23 words
The semiconductor memory device of claim 1 wherein said semiconductor memory means is a memory element in a write-once, read-only semiconductor memory array.
Claim 6
Dependent Claim
45 words
The semiconductor memory device of claim 4 wherein said "0" memory state representative of said conducting state of memory is created after a write-once operation provides said voltage at least equal to said breakdown voltage to said electrode means coupled to said semiconductor memory means.
Claim 7
Dependent Claim
45 words
The semiconductor memory device of claim 4 wherein said "1" memory state representative of said conducting state of memory is created after a write-once operation provides said voltage at least equal to said breakdown voltage to said electrode means coupled to said semiconductor memory means.
Claim 8
Dependent Claim
80 words
The semiconductor memory device of claim 1 wherein said electrode means comprising a first electrode and a second electrode, said first electrode is a first primarily metal electrode coupled to one portion of said semiconductor memory means, said second electrode is said at least one electrode having said ohmic contact which comprises a second primarily metal electrode coupled to another portion of said semiconductor memory means and in electrical contact with said doped semiconductor region located in said semiconductor substrate.
Claim 9
Dependent Claim
22 words
The semiconductor memory device of claim 7 wherein said first electrode is an AlSiCu electrode, said second electrode is a MoSi electrode.
Claim 10
Dependent Claim
24 words
The semiconductor memory device of claim 7 wherein said first electrode is a MoSi electrode and said second electrode in also a MoSi electrode.
Claim 11
Dependent Claim
25 words
The semiconductor memory device of claim 9 wherein said doped semiconductor region is of N+ type conductivity and said substrate is of P- type conductivity.
Claim 12
Dependent Claim
21 words
The semiconductor memory device of claim 7 wherein a third primarily metal electrode is electrically connected to said doped semiconductor region.
Claim 13
Dependent Claim
20 words
The semiconductor memory device of claim 11 wherein a fourth primarily metal electrode is electrically connected to said semiconductor substrate.
Claim 14
Dependent Claim
344 words
A write-once, read-only semiconductor memory array comprising, in combination: a plurality of semiconductor memory cell elements interconnected to provide said semiconductor memory array, each one of said plurality of semiconductor memory cell elements comprising a semiconductor substrate having a doped semiconductor region and a dielectric layer on one surface thereof and at least one opening located in said dielectric layer to permit electrical contact to be made to said doped semiconductor region; a primarily metal ohmic contact located in said opening and in electrical ohmic contact with said doped semiconductor region of said semiconductor substrate; semiconductor memory means in contact with said ohmic contact and having a-silicon material for providing a non-conducting state of memory representative of one of a "1" and "0" memory state when said a-silicon material functions as an insulator and for providing a conducting state of memory representative of the other of said "1" and "0" memory state when said a-silicon material functions as an electrical conductor; writing means coupled to each one of said plurality of semiconductor memory cell elements for selectively providing a write-once operation to any of said plurality of semiconductor memory cell elements by applying a voltage at least equal to a preselected breakdown voltage to said any of said plurality of semiconductor memory cell elements, said writing means comprising electrode means including said ohmic contact and said doped semiconductor region as one electrode coupled to said semiconductor memory means of each of said plurality of semiconductor memory cell elements for selectively applying thereto one of a voltage below said preselected breakdown voltage to maintain said a-silicon material in said non-conducting state of memory and said voltage at least equal to said preselected breakdown voltage to place said a-silicon material in said conducting state of memory; and reading means coupled to each one of said plurality of semiconductor memory cell elements for sensing which of said plurality of semiconductor memory cell elements is in said conducting state of memory and which of said plurality of semiconductor memory cell elements is in said non-conducting state of memory.
Claim 15
Dependent Claim
344 words
A write-once, read-only semiconductor memory array comprising, in combination: a plurality of semiconductor memory cell elements interconnected to provide said semiconductor memory array, each one of said plurality of semiconductor memory cell elements comprising a semiconductor substrate having a doped semiconductor region and a dielectric layer on one surface thereof and at least one opening located in said dielectric layer to permit electrical contact to be made to said doped semiconductor region; a primarily metal ohmic contact located in said opening and in electrical ohmic contact with said doped semiconductor region of said semiconductor substrate; semiconductor memory means in contact with said ohmic contact and having a-silicon material for providing a non-conducting state of memory representative of one of a "1" and "0" memory state when said a-silicon material functions as an insulator and for providing a conducting state of memory representative of the other of said "1" and "0" memory state when said a-silicon material functions as an electrical conductor; writing means coupled to each one of said plurality of semiconductor memory cell elements for selectively providing a write-once operation to any of said plurality of semiconductor memory cell elements by applying a voltage at least equal to a preselected breakdown voltage to said any of said plurality of semiconductor memory cell elements, said writing means comprising electrode means including said ohmic contact and said doped semiconductor region as one electrode coupled to said semiconductor memory means of each of said plurality of semiconductor memory cell elements for selectively applying thereto one of a voltage below said preselected breakdown voltage to maintain said a-silicon material in said non-conducting state of memory and said voltage at least equal to said preselected breakdown voltage to place said a-silicon material in said conducting state of memory; and reading means coupled to each one of said plurality of semiconductor memory cell elements for sensing which of said plurality of semiconductor memory cell elements is in said conducting state of memory and which of said plurality of semiconductor memory cell elements is in said non-conducting state of memory.
Claim 16
Dependent Claim
31 words
The write-once, read-only semiconductor memory array of claim 13 wherein said non-conducting state of memory is said "1" memory state and said conducting state of memory is said "0" memory state.
Claim 17
Dependent Claim
31 words
The write-once, read-only semiconductor memory array of claim 13 wherein said non-conducting state of memory is said "0" memory state and said conducting state of memory is said "1" memory state.
Claim 18
Dependent Claim
47 words
The write-once, read-only semiconductor memory array of claim 14 wherein said "0" memory state representative of said conducting state of memory is created after said write-once operation provides said voltage at least equal to said breakdown voltage to said electrode, means coupled to said semiconductor memory means.
Claim 19
Dependent Claim
47 words
The write-once, read-only semiconductor memory array of claim 15 wherein said "1" memory state representative of said conducting state of memory is created after said write-once operation provides said voltage at least equal to said breakdown voltage to said electrode means coupled to said semiconductor memory means.
Claim 20
Dependent Claim
82 words
The write-once, read-only semiconductor memory array of claim 13 wherein said electrode means comprising a first electrode and a second electrode, said first electrode is a first primarily metal electrode coupled to one portion of said semiconductor memory means, said second electrode is said at least one electrode having said ohmic contact which comprises a second primarily metal electrode coupled to another portion of said semiconductor memory means and in electrical contact with said doped semiconductor region located in said semiconductor substrate.
Claim 21
Dependent Claim
24 words
The write-once, read-only semiconductor memory array of claim 18 wherein said first electrode is an AlSiCu electrode, said second electrode is a MoSi electrode.
Claim 22
Dependent Claim
26 words
The write-once, read-only semiconductor memory array of claim 18 wherein said first electrode is a MoSi electrode and said second electrode in also a MoSi electrode.
Claim 23
Dependent Claim
27 words
The write-once, read-only semiconductor memory array of claim 20 wherein said doped semiconductor region is of N+ type conductivity and said substrate is of P- type conductivity.
Claim 24
Dependent Claim
23 words
The write-once, read-only semiconductor memory array of claim 18 wherein a third primarily metal electrode is electrically connected to said doped semiconductor region.
Claim 25
Dependent Claim
22 words
The write-once, read-only semiconductor memory array of claim 22 wherein a fourth primarily metal electrode is electrically connected to said semiconductor substrate.
References Cited (Backward Citations)
US5406509A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |