US5455954A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Host interrupt signal generation circuit for controlling an auto read operation in a disk drive controller
Assignee: STMicroelectronics NV
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Filing: 1993-12-22
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Granted: 1995-10-03
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Expires: 2013-12-22
Abstract
Abstract A host interface uses a state machine to control multiple sector transfers between a host computer and a physical storage medium, so that the idle time between sector transfers is minimized and not a function of the local microprocessor. A write sector counter is provided to keep track of the largest segment in a buffer memory so that demands for the local microprocessor is minimized. In addition, start counters pointing at the next sector in the buffer memory are provided to shorten response time in a read cache. BUSY and IRQ timers are provided to accommodate various implementations of BIOS's which may inadvertently clear a host interrupt to lead to a failure condition.
Inventors
- 👤 John S. Packer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
211 words
In a disk controller communicating with a host computer over an AT bus, a method for setting a host interrupt during a READ command transferring multiple groups of data, said method comprising the steps of: providing, in said disk controller, a host interrupt generation circuit coupled to said AT bus for asserting an IRQ signal on an interrupt line of said AT bus, asserting, using said host interrupt generation circuit, a first host interrupt IRQ signal on said interrupt line to initiate a transfer to said host computer a first group of said data; transferring said first group of data between said disk controller and said host computer; and asserting, using said host interrupt generation circuit, upon occurrence of an event, a second host interrupt IRQ signal on said interrupt line to initiate a transfer to said host computer a second group of said data upon occurrence of an event, said event being configurable to occur under a selected one of the following conditions: (i) elapse of a predetermined time interval according to a timer, (ii) the earlier of either (a) said host computer reading an AT status register, or (b) elapse of said predetermined time interval according to said timer, and (iii) said host computer reading said AT status register.
Claim 2
Dependent Claim
211 words
In a disk controller communicating with a host computer over an AT bus, a method for setting a host interrupt during a READ command transferring multiple groups of data, said method comprising the steps of: providing, in said disk controller, a host interrupt generation circuit coupled to said AT bus for asserting an IRQ signal on an interrupt line of said AT bus, asserting, using said host interrupt generation circuit, a first host interrupt IRQ signal on said interrupt line to initiate a transfer to said host computer a first group of said data; transferring said first group of data between said disk controller and said host computer; and asserting, using said host interrupt generation circuit, upon occurrence of an event, a second host interrupt IRQ signal on said interrupt line to initiate a transfer to said host computer a second group of said data upon occurrence of an event, said event being configurable to occur under a selected one of the following conditions: (i) elapse of a predetermined time interval according to a timer, (ii) the earlier of either (a) said host computer reading an AT status register, or (b) elapse of said predetermined time interval according to said timer, and (iii) said host computer reading said AT status register.
Claim 3
Dependent Claim
194 words
In a disk controller communicating with a host computer over an AT bus, including a transfer circuit for transferring groups of data between said disk controller and said host computer, a host interrupt generation circuit for setting a host interrupt IRQ signal on an interrupt line of said AT bus during a READ command transferring multiple groups of data comprising: a first circuit for asserting a first host interrupt IRQ signal on said interrupt line to initiate transfer by said transfer circuit to said host computer a first group of said data; and a second circuit including a timer for asserting, upon occurrence of an event, a second host interrupt IRQ signal on said interrupt line to initiate a transfer by said transfer circuit to said host computer a second group of said data, said event being configurable to occur under a selected one of the following conditions: (i) elapse of a predetermined time interval according to said timer, (ii) the earlier of either (a) said host computer reading an AT status register, or (b) elapse of said predetermined time interval according to said timer, and (iii) said computer reading said AT status register.
Claim 4
Dependent Claim
194 words
In a disk controller communicating with a host computer over an AT bus, including a transfer circuit for transferring groups of data between said disk controller and said host computer, a host interrupt generation circuit for setting a host interrupt IRQ signal on an interrupt line of said AT bus during a READ command transferring multiple groups of data comprising: a first circuit for asserting a first host interrupt IRQ signal on said interrupt line to initiate transfer by said transfer circuit to said host computer a first group of said data; and a second circuit including a timer for asserting, upon occurrence of an event, a second host interrupt IRQ signal on said interrupt line to initiate a transfer by said transfer circuit to said host computer a second group of said data, said event being configurable to occur under a selected one of the following conditions: (i) elapse of a predetermined time interval according to said timer, (ii) the earlier of either (a) said host computer reading an AT status register, or (b) elapse of said predetermined time interval according to said timer, and (iii) said computer reading said AT status register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |