Digital computer system having circuit for regulation of I/O command recovery time

Claim 1

A digital computer system, having a central processor unit (CPU), a plurality of addressable input/output (I/O) peripheral devices connected thereto for accessing by the digital computer system through I/O commands, at least one of the plurality of I/O peripheral devices requiring a corresponding access recovery time, comprising: (a) decoding means for receiving the I/O commands and the addresses of the associated I/O peripheral devices from the CPU and having an output; (b) time duration circuitry for providing a recovery request signal for those peripheral devices requiring access recovery times of a time duration determined by the combination of I/O commands and the addresses of the associated I/O peripheral devices from the output of the decoding means, and for providing no recovery request signal for those devices not requiring access recovery time; and (c) a bus controller connected to the CPU for receiving the recovery request signal from the time duration circuitry and generating a hold signal in response to the recovery request signal for transmission to the CPU to prevent entry into the decoding means of any subsequent I/O commands in the presence of the hold signal, the duration of which is determined by the length of the recovery request signal from the time duration circuitry, and to allow entry of I/O commands into the decoding means in the absence of the hold signal.