US4393446A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Routine timer for computer systems
Assignee: General Electric Co
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Filing: 1981-04-27
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Granted: 1983-07-12
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Expires: 2001-04-27
Abstract
Abstract The processing of computer program delays and timers is placed outside the computer mainframe in a routine timer in order to reduce the amount of computer processing capability dedicated to keeping track of time intervals to be performed by the computer. Such a routine is particularly applicable to systems controlling a plurality of devices in which each device is controlled by a separate computer program designed to operate the device in a predetermined manner in response to specific conditions detected at the hardware site and transmitted to the computer.
Inventors
- 👤 George P. Gurr
- 👤 Robert M. Hardy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4825; G06F11/00; G06F11/30; G06F11/3003; G06F11/3017; G06F11/3055; G06F11/34; G06F11/3409; G06F11/3419; G06F2201/00; G06F2201/88
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
221 words
A method of processing routine delays for a main computer, including a main memory, monitoring a plurality of hardware devices operating simultaneously and controlling real-time tasks of said hardware devices according to a plurality of preprogrammed process routines stored in a main memory including a respective routine for each real-time task, comprising the steps of: identifying each of a plurality of process routines for servicing one of a plurality of real-time tasks, respectively, to be controlled by the main computer with a unique identifier which said main computer is programmed to recognize; supplying task data from said plurality of devices to be received by said main computer for use in a plurality of identified process routines; processing said process routines in said main computer in order of a predetermined priority stored in a table in the main memory until a predetermined memory address is accessed by the routine currently being processed, thereby activating a routine delay and stopping processing of said routine undergoing processing by the main computer; transferring processing of said routine having been stopped to a routine timer located outside said main computer, said routine timer having a data analysis control means for processing said delay simultaneous with other routine delays; and after said delay is terminated, returning processing of the routine having been stopped to said main computer.
Claim 2
Independent Claim
221 words
A method of processing routine delays for a main computer, including a main memory, monitoring a plurality of hardware devices operating simultaneously and controlling real-time tasks of said hardware devices according to a plurality of preprogrammed process routines stored in a main memory including a respective routine for each real-time task, comprising the steps of: identifying each of a plurality of process routines for servicing one of a plurality of real-time tasks, respectively, to be controlled by the main computer with a unique identifier which said main computer is programmed to recognize; supplying task data from said plurality of devices to be received by said main computer for use in a plurality of identified process routines; processing said process routines in said main computer in order of a predetermined priority stored in a table in the main memory until a predetermined memory address is accessed by the routine currently being processed, thereby activating a routine delay and stopping processing of said routine undergoing processing by the main computer; transferring processing of said routine having been stopped to a routine timer located outside said main computer, said routine timer having a data analysis control means for processing said delay simultaneous with other routine delays; and after said delay is terminated, returning processing of the routine having been stopped to said main computer.
Claim 3
Dependent Claim
40 words
The method of claim 1 further comprising maintaining an updated routine priority table in said main memory wherein each routine status is entered according to activity within said main computer and updating said routine status when a delay is terminated.
Claim 4
Dependent Claim
90 words
The method of claim 2 wherein said step of processing routine delays comprises establishing a memory location for storing a time duration for each delay in said data analysis control means of said routine timer, decrementing said time duration for each said delay, respectively, by successive predetermined time segments at regular predetermined time intervals equal in length to said time segments; and returning processing of each of said delayed routines to said main computer, respectively, after said time duration for each said delayed routine, respectively, has been decremented to zero.
Claim 5
Dependent Claim
13 words
The method of claim 3 wherein said predetermined time segment equals 200 microseconds.
Claim 6
Dependent Claim
61 words
The method of claim 3 wherein said step of returning said routine processing of each of said delayed routines, respectively, to said main computer after said respective delay has terminated comprises the step of delaying said returning of said routine processing in response to an instruction from said routine timer to complete decrementing all delayed routines by said predetermined time segment.
Claim 7
Dependent Claim
14 words
The method of claim 5 wherein all routine delays are decremented within 200 microseconds.
Claim 8
Dependent Claim
27 words
The method of claim 1 wherein said transferring of processing to and from the routine timer is controlled by an input/output control means within said routine timer.
Claim 9
Dependent Claim
56 words
The method of claim 1 wherein said step of processing routine delays comprises decrementing each delay during each said predetermined time interval and postponing, if necessary, return of processing to routines having terminated delays to said main computer so that said decrementing for all routine delays can be completed within a time equal to said interval.
Claim 10
Dependent Claim
77 words
The method of claim 8 wherein said step of postponing return of routine processing to routines having terminated delays to said main computer comprises checking a flag indicative of time remaining in said predetermined time interval, comparing said remaining time with a signal indicative of the time required to complete decrementing of all routine delays, and not returning processing of terminated delays if not enough time remains to decrement all routine delays in said predetermined time interval.
Claim 11
Independent Claim
200 words
A method of processing timers of a main computer including a main memory monitoring a plurality of hardware devices operating simultaneously and controlling real-time tasks of said hardware devices according to a plurality of preprogrammed process routines stored in a main memory including a respective routine for each real-time task, comprising the steps of: identifying each of a plurality of process routines for servicing one of a plurality of real-time tasks, respectively, to be controlled by the main computer with a unique identifier which said main computer is programmed to recognize; supplying task data from said plurality of devices to be received by said main computer for use in a plurality of identified process routines; processing said process routines in said main computer in order of a predetermined priority stored in a table in the main memory until an event timer is initiated by accessing a predetermined memory addressed by the routine currently being processed; transferring processing of said timer to a routine timer located outside said main computer, said routine timer having a data analysis control means for processing said timer simultaneously with other active timers; and after said timer is terminated, setting a flag in said main computer.
Claim 12
Independent Claim
200 words
A method of processing timers of a main computer including a main memory monitoring a plurality of hardware devices operating simultaneously and controlling real-time tasks of said hardware devices according to a plurality of preprogrammed process routines stored in a main memory including a respective routine for each real-time task, comprising the steps of: identifying each of a plurality of process routines for servicing one of a plurality of real-time tasks, respectively, to be controlled by the main computer with a unique identifier which said main computer is programmed to recognize; supplying task data from said plurality of devices to be received by said main computer for use in a plurality of identified process routines; processing said process routines in said main computer in order of a predetermined priority stored in a table in the main memory until an event timer is initiated by accessing a predetermined memory addressed by the routine currently being processed; transferring processing of said timer to a routine timer located outside said main computer, said routine timer having a data analysis control means for processing said timer simultaneously with other active timers; and after said timer is terminated, setting a flag in said main computer.
Claim 13
Dependent Claim
82 words
The method of claim 10 wherein said step of processing timers comprises establishing a memory location for storing a time duration for each timer, in said data analysis control means of said routine timer, decrementing said time duration for each said timer, respectively, by successive predetermined time segments at a regular predetermined time intervals equal in length to said time segments; and setting a flag in said main computer after said time duration for each said timer has been decremented to zero.
Claim 14
Dependent Claim
13 words
The method of claim 11 wherein said predetermined time segment equals 200 microseconds.
Claim 15
Dependent Claim
50 words
The method of claim 11 wherein said step of setting a flag in said main computer after said timer has terminated comprises the step of delaying said setting of the flag in response to an instruction from said routine timer to complete decrementing all timers by said predetermined time segment.
Claim 16
Dependent Claim
199 words
A computer system for providing real-time servicing to a plurality of hardware devices comprising: a main computer forprocessing a plurality of preprogrammed routines for servicing respective ones of said hardware devices; a main memory coupled to said main computer to exchange data back and forth; a routine timer located outside said main computer for simultaneously processing event timers called for by said preprogrammed routines run in said main computer simultaneously, said routine timer comprising means for monitoring said main computer during processing of said plurality of routines to detect predetermined memory access associated with said routines being processed; input/output control means for sequencing the transfer of data containing the length of an event timer called for by a specific routine from said main memory to said input/output control means and for providing signals indicative of event timer termination of a specific event timer to said main memory; data analysis control means for processing information provided by said input/output control means by decrementing each event timer by a predetermined time segment and informing said input/output control when an event timer has terminated; and means to control transfer of information between said input/output control means and said data analysis control means.
Claim 17
Dependent Claim
199 words
A computer system for providing real-time servicing to a plurality of hardware devices comprising: a main computer forprocessing a plurality of preprogrammed routines for servicing respective ones of said hardware devices; a main memory coupled to said main computer to exchange data back and forth; a routine timer located outside said main computer for simultaneously processing event timers called for by said preprogrammed routines run in said main computer simultaneously, said routine timer comprising means for monitoring said main computer during processing of said plurality of routines to detect predetermined memory access associated with said routines being processed; input/output control means for sequencing the transfer of data containing the length of an event timer called for by a specific routine from said main memory to said input/output control means and for providing signals indicative of event timer termination of a specific event timer to said main memory; data analysis control means for processing information provided by said input/output control means by decrementing each event timer by a predetermined time segment and informing said input/output control when an event timer has terminated; and means to control transfer of information between said input/output control means and said data analysis control means.
Claim 18
Dependent Claim
190 words
A computer system for providing realtime servicing to a plurality of hardware devices comprising: a main computer for processing a plurality of preprogrammed routines for servicing respective ones of said hardware devices; a main memory coupled to said main computer to exchange data back and forth; a routine timer located outside said main computer for simultaneously processing delays called for by said preprogrammed routines run in said main computer, said routine timer comprising means for monitoring said main computer during processing of said plurality of routines to detect predetermined memory access associated with said routines being processed; input/output control means for sequencing the transfer of data containing length of a delay of a specific routine from said main memory to said input/output control means and for providing signals indicative of delay termination of a specific delay to said main memory; data analysis control means for processing information provided by said input/output control means by decrementing each delay by a predetermined time segment and informing said input/output control when a delay has terminated; and means to control transfer of information between said input/output control means and said data analysis control means.
Claim 19
Dependent Claim
190 words
A computer system for providing realtime servicing to a plurality of hardware devices comprising: a main computer for processing a plurality of preprogrammed routines for servicing respective ones of said hardware devices; a main memory coupled to said main computer to exchange data back and forth; a routine timer located outside said main computer for simultaneously processing delays called for by said preprogrammed routines run in said main computer, said routine timer comprising means for monitoring said main computer during processing of said plurality of routines to detect predetermined memory access associated with said routines being processed; input/output control means for sequencing the transfer of data containing length of a delay of a specific routine from said main memory to said input/output control means and for providing signals indicative of delay termination of a specific delay to said main memory; data analysis control means for processing information provided by said input/output control means by decrementing each delay by a predetermined time segment and informing said input/output control when a delay has terminated; and means to control transfer of information between said input/output control means and said data analysis control means.
Claim 20
Dependent Claim
31 words
The apparatus of claim 15 wherein said routine timer further comprises a real-time clock to control the decrementing of each respective routine delay in a series of successive equal time segments.
Claim 21
Dependent Claim
22 words
The apparatus of claim 15 further comprising means for uniquely locating each routine delay within the routine timer at a given time.
Claim 22
Dependent Claim
29 words
The apparatus of claim 17 further comprising means for cancelling a routine delay being processed by said routine timer responsive to changes in conditions of said external hardware devices.
Claim 23
Dependent Claim
32 words
The apparatus of claim 18 further comprising means for updating the length of a routine delay being processed by said routine timer responsive to changes in conditions of said external hardware devices.
Claim 24
Dependent Claim
55 words
The apparatus of claim 19 wherein said means for controlling transfer of information between said input/output control means and said data analysis control means comprises resettable indicator means for providing at least one flag whose state is established by said input/output control means to be read by said data analysis control means and vice versa.
Claim 25
Dependent Claim
35 words
The apparatus of claim 20 wherein said input/output control means includes means to retain data to be transferred to said main computer while said data analysis controller completes decrementing of each of said routine delays.
Claim 26
Dependent Claim
23 words
The computer system of claim 15 wherein said main memory includes a predetermined priority table of the preprogrammed routines and their delay status.
Claim 27
Dependent Claim
35 words
The computer system of claim 22 wherein said transfer of data to the input/output control means concerning a particular routine delay further includes the address in the priority table corresponding to the preprogrammed routine delayed.
Claim 28
Dependent Claim
30 words
The computer system of claim 23 wherein said signals indicative of a delay termination of a specific delay alters the status of the associated preprogrammed routine in the priority table.
Claim 29
Dependent Claim
210 words
A computer system for providing realtime servicing to a plurality of hardware devices comprising: a main computer for processing a plurality of preprogrammed routines for servicing respective ones of said hardware devices; a main memory coupled to said main computer to exchange data back and forth; a routine timer located outside said main computer for simultaneously processing delays and event timers called for by said preprogrammed routines run in said main computer, said routine timer comprising means for monitoring said main computer during processing of said plurality of routines to detect predetermined memory access associated with said routines being processed; input/output control means for sequencing the transfer of data containing the length of a delay and length of an event timer of a specific routine from said main memory to said input/output control means and for providing signals indicative of delay and event timer termination to said main memory; data analysis control means for processing information provided by said input/output control means by decrementing each delay and each event timer by a predetermined time segment and informing said input/output control when a delay has terminated and when an event timer has terminated; and means to control transfer of information between said input/output control means and said data analysis control means.
Claim 30
Dependent Claim
210 words
A computer system for providing realtime servicing to a plurality of hardware devices comprising: a main computer for processing a plurality of preprogrammed routines for servicing respective ones of said hardware devices; a main memory coupled to said main computer to exchange data back and forth; a routine timer located outside said main computer for simultaneously processing delays and event timers called for by said preprogrammed routines run in said main computer, said routine timer comprising means for monitoring said main computer during processing of said plurality of routines to detect predetermined memory access associated with said routines being processed; input/output control means for sequencing the transfer of data containing the length of a delay and length of an event timer of a specific routine from said main memory to said input/output control means and for providing signals indicative of delay and event timer termination to said main memory; data analysis control means for processing information provided by said input/output control means by decrementing each delay and each event timer by a predetermined time segment and informing said input/output control when a delay has terminated and when an event timer has terminated; and means to control transfer of information between said input/output control means and said data analysis control means.
Claim 31
Dependent Claim
33 words
The apparatus of claim 25 wherein said routine timer further comprises a real-time clock to control the decrementing of each respective routine delay and timer in a series of successive equal time segments.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-11 | 1987-01-10 | 1987-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-11 | 1991-01-10 | 1991-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-11 | 1995-01-10 | 1995-07-12 | $7700.00 | Window Closed / Lapsed |