Computer system with bridge circuitry having input/output multiplexers and third direct unidirectional path for data transfer between buses operating at different rates

Claim 1

A computer system comprising: a central processing unit (CPU) having a characteristic operating speed; a main memory; a first bus operating at a first rate that approximates the characteristic operating speed of the CPU, the first bus being coupled to the CPU and the main memory; a first bus master coupled to the first bus; a secondary bus operating at a second rate which is substantially slower than the first rate; a second bus master coupled to the secondary bus; a device for storing data coupled to the secondary bus; a bridge circuit for transferring information between the first and the secondary buses comprising address and data circuits, said bridge circuit includes: a first unidirectional path including a line buffer; a second unidirectional path including a write buffer; a third direct unidirectional path; first multiplexer (MUX) means for coupling input address/data information from either the first or secondary buses to either the first, second or third unidirectional paths; second multiplexer (MUX) means for coupling output address/data information from either the first, second or third unidirectional paths to either the first or secondary buses; bus arbitration circuitry for arbitrating access to the first and secondary buses and for controlling the first and second MUX means; in an event of a read request by the second bus master to the main memory, the bus arbitration circuitry causing the first MUX means of the address circuit to store a read address provided by the second bus master in the line buffer, then, using the read address stored in the line buffer, the bus arbitration circuitry initiating a read cycle such that the second MUX means transfers read data from the main memory onto the first bus, the bus arbitration circuitry thereafter causing the first MUX means of the data circuit to store the read data in the line buffer and then cause the second MUX means to transfer the read data to the secondary bus.