US5455732A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buffer protection against output-node voltage excursions
Assignee: Fairchild Semiconductor Corp
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Filing: 1993-09-15
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Granted: 1995-10-03
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Expires: 2013-09-15
Abstract
Abstract A three-state output buffer circuit with built-in protection against power-rail corruption by bus-imposed voltages when the buffer is in its high-impedance state. In particular the invention protects the high-potential power rail of the high-Z buffer against voltages appearing at the buffer's output node which exceed the voltage of the buffer's high-potential rail. It prevents this overvoltage from finding its way to the power-rail, and thus has application to those situations where a common bus is coupled to a variety of circuits including, for example, 3.3-volt buffers and 5-volt buffers. The invention provides this protection without the "dead zone" of prior-art and related-art circuits. Furthermore, the present invention also has application where it is the low-potential power rail that needs protecting, in situations where the bus may impose voltages at the buffer's output node that are lower than the voltage of the buffer's low-potential power rail. The protection circuit utilizes a pseudo-power rail which can be used to adjust the bias on the output transistor's bulk and so to prevent a leakage path from occurring between the output node and a power rail via the output transistor source/bulk junction. To minimize or avoid a "dead zone" in the charging of the pseudo-rail, a one-way link is established directly between the power rail and the pseudo-power-rail.
Inventors
- 👤 Jeffery B. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/00315
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
178 words
Protective circuit apparatus for guarding an output transistor and a power rail of an output buffer against voltages applied to an output node of said buffer, said apparatus comprising (a) a comparator with a plurality of comparator inputs and a comparator output, (b) a pseudo-power-rail, (c) a one-way link having a positive node and a negative node such that current can flow only from said positive node to said negative node and then only when said positive node is at a positive voltage with respect to said negative node, wherein said pseudo-power-rail is connected: (i) to said comparator output, (ii) to a bulk node of said output transistor, and (iii) to said negative node of said one-way link, wherein a first of said comparator inputs is connected to said power rail, wherein a second of said comparator inputs is connected to said output node, and wherein said comparator couples to said comparator output whichever of said comparator inputs is at a higher voltage, and wherein said positive node of said one-way link is connected to said power rail.
Claim 2
Dependent Claim
178 words
Protective circuit apparatus for guarding an output transistor and a power rail of an output buffer against voltages applied to an output node of said buffer, said apparatus comprising (a) a comparator with a plurality of comparator inputs and a comparator output, (b) a pseudo-power-rail, (c) a one-way link having a positive node and a negative node such that current can flow only from said positive node to said negative node and then only when said positive node is at a positive voltage with respect to said negative node, wherein said pseudo-power-rail is connected: (i) to said comparator output, (ii) to a bulk node of said output transistor, and (iii) to said negative node of said one-way link, wherein a first of said comparator inputs is connected to said power rail, wherein a second of said comparator inputs is connected to said output node, and wherein said comparator couples to said comparator output whichever of said comparator inputs is at a higher voltage, and wherein said positive node of said one-way link is connected to said power rail.
Claim 3
Dependent Claim
42 words
Protective circuit apparatus as described in claim 1 also comprising a feedback transistor coupled between said pseudo-power-rail and a gate node of said output transistor, wherein a gate node of said feedback transistor is connected to an enable input of said buffer.
Claim 4
Dependent Claim
92 words
Protective circuit apparatus as described in claim 2 also comprising a first driver transistor and a first blocker transistor, wherein said first driver transistor is connected in series with said first blocking transistor to form a first driver/blocker combination, wherein said first driver/blocker combination is connected between said power rail and said gate of said output transistor, wherein a gate node of said first driver transistor is connected to a data input node of said buffer, and wherein a gate node of said first blocker transistor is connected to said power rail.
Claim 5
Dependent Claim
77 words
Protective circuit apparatus as described in claim 3 also comprising a second driver transistor connected in series with a second blocker transistor to form a second driver/blocker combination, wherein said second driver/blocker combination is connected between said power rail and said gate of said output transistor, wherein a gate node of said second driver transistor is connected to said enable input, and wherein a gate node of said second blocker transistor is connected to said power rail.
Claim 6
Dependent Claim
75 words
Protective circuit apparatus as described in claim 1 wherein said comparator includes a first passgate transistor and a second passgate transistor, wherein said first passgate transistor is connected between said bulk node of said output transistor and a gate node of said second passgate transistor, wherein a gate node of said first passgate transistor is connected to said output node, and wherein said second passgate transistor is coupled between said output node and said pseudo-power-rail.
Claim 7
Dependent Claim
39 words
Protective circuit apparatus as described in claim 5 wherein said one-way link includes a MOS linking transistor coupled between said power rail and said pseudo-power-rail, wherein a gate node of said linking transistor is coupled to said power rail.
Claim 8
Dependent Claim
57 words
Protective circuit apparatus as described in claim 6 wherein said output transistor is a PMOS output pullup transistor, said power rail is a high-potential power rail, said pseudo-power-rail is a pseudo-high-potential-power-rail, said first passgate transistor is a PMOS transistor, said second passgate transistor is a PMOS transistor, and said MOS linking transistor is a low-transition-voltage NMOS transistor.
Claim 9
Dependent Claim
57 words
Protective circuit apparatus as described in claim 6 wherein said output transistor is an NMOS output pulldown transistor, said power rail is a low-potential power rail, said pseudo-power-rail is a pseudo-low-potential-power-rail, said first passgate transistor is an NMOS transistor, said second passgate transistor is an NMOS transistor, and said MOS linking transistor is a low-transition-voltage PMOS transistor.
Claim 10
Dependent Claim
84 words
An output buffer incorporating a high-potential power rail guarded against overvoltages on an output node, said buffer comprising (a) a comparator with a plurality of comparator inputs, one of which is connected to said output node and one of which is connected to said high-potential power rail, and a comparator output, (b) a pseudo-high-potential-power-rail couple to a bulk node of a PMOS output pullup transistor, and to said comparator output, and (c) a one-way link coupling said pseudo-high-potential-power rail to said high-potential power rail.
Claim 11
Dependent Claim
84 words
An output buffer incorporating a high-potential power rail guarded against overvoltages on an output node, said buffer comprising (a) a comparator with a plurality of comparator inputs, one of which is connected to said output node and one of which is connected to said high-potential power rail, and a comparator output, (b) a pseudo-high-potential-power-rail couple to a bulk node of a PMOS output pullup transistor, and to said comparator output, and (c) a one-way link coupling said pseudo-high-potential-power rail to said high-potential power rail.
Claim 12
Dependent Claim
71 words
Buffer as described in claim 9 wherein said comparator includes a first transistor passgate and a second transistor passgate, wherein said first passgate is connected between said bulk of said pullup transistor and a gate node of said second passgate transistor, wherein a gate node of said first passgate transistor is connected to said output node, and wherein said second passgate transistor is connected between said output node and said pseudo-high-potential-power-rail.
Claim 13
Dependent Claim
38 words
Buffer as described in claim 10 wherein said one-way link is an NMOS linking transistor coupled between said high-potential power rail and said pseudo-high-potential-power-rail, wherein a gate node of said linking transistor is connected to said high-potential-power rail.
Claim 14
Dependent Claim
19 words
Buffer as described in claim 11 wherein said linking transistor is manufactured to have an extremely low transition voltage.
Claim 15
Dependent Claim
40 words
Buffer as described in claim 12 having a PMOS feedback transistor coupled between said pseudo-high-potential-power-rail and a gate node of said pullup transistor, wherein a gate node of said feedback transistor is connected to an enable input of said buffer.
Claim 16
Dependent Claim
114 words
Buffer as described in claim 13 having a first PMOS driver transistor and a first NMOS blocker transistor, wherein a source node of said first PMOS driver transistor is connected to said high-potential power rail, wherein a drain node of said first PMOS driver transistor is connected to a drain node of said first NMOS blocker transistor, wherein a source node of said first NMOS blocker transistor is connected to said gate node of said pullup transistor, wherein a gate node of said first PMOS driver transistor is connected to a data input of said buffer, and wherein a gate node of said first NMOS blocker transistor is connected to said high-potential power rail.
Claim 17
Dependent Claim
111 words
Buffer as described in claim 14 having a second PMOS driver transistor and a second NMOS blocker transistor, wherein a source node of said second PMOS driver transistor is connected to said high-potential power rail, wherein a drain of said second PMOS driver transistor is connected to a drain node of said second NMOS blocker transistor, wherein a source node of said second NMOS blocker transistor is connected to said gate node of said pullup transistor, wherein a gate node of said second PMOS driver transistor is connected to an enable input node, and wherein a gate node of said second NMOS blocker transistor is connected to said high-potential power rail.
Claim 18
Dependent Claim
155 words
Buffer as described in claim 15 having a third NMOS blocker transistor, a first PMOS isolating transistor and an NMOS disabling transistor, wherein said source node of said second NMOS blocker transistor is connected to a drain node of said third NMOS blocker transistor, wherein said source node of said third NMOS blocker transistor is connected to a source node of said first PMOS isolating transistor, wherein a drain of said first PMOS isolating transistor is connected to a drain node of said NMOS disabling transistor, wherein a source node of said NMOS disabling transistor is connected to a low potential power rail, and wherein a gate node of said third NMOS blocker transistor is coupled to said high potential power rail, a gate node of said first PMOS blocker transistor is coupled to an disabler input node, and wherein a gate node of said NMOS disabling transistor is connected to said disabler input node.
Claim 19
Dependent Claim
44 words
A buffer as described in claim 16 also comprising an output pulldown transistor connected between said output node and said low potential power rail wherein a gate node of said output pulldown transistor is connected to a drain node of said NMOS disabling transistor.
Claim 20
Dependent Claim
83 words
An output buffer incorporating a low-potential power rail guarded against undervoltages on an output node, said buffer comprising, (a) a comparator with a plurality of comparator inputs, one of which is connected to said output node and one of which is connected to said low-potential power rail, and a comparator output, (b) a pseudo-low-potential-power-rail coupled to a bulk node of an NMOS output pulldown transistor, and to said comparator output, and (c) a one-way link coupling said pseudo-low-potential-power-rail to said low-potential power rail.
Claim 21
Dependent Claim
83 words
An output buffer incorporating a low-potential power rail guarded against undervoltages on an output node, said buffer comprising, (a) a comparator with a plurality of comparator inputs, one of which is connected to said output node and one of which is connected to said low-potential power rail, and a comparator output, (b) a pseudo-low-potential-power-rail coupled to a bulk node of an NMOS output pulldown transistor, and to said comparator output, and (c) a one-way link coupling said pseudo-low-potential-power-rail to said low-potential power rail.
Claim 22
Dependent Claim
73 words
Buffer as described in claim 18 wherein said comparator includes a first passgate transistor and a second passgate transistor, wherein said first passgate transistor is connected between said bulk of said pulldown transistor and a gate node of said second passgate transistor, wherein a gate node of said first passgate transistor is connected to said output node, and wherein said second passgate transistor is connected between said output node and said pseudo-low-potential power-rail.
Claim 23
Dependent Claim
136 words
An output-buffer-power-rail-protecting method for guarding a high-potential power rail of an inactive-state output buffer against overvoltages on an output node of said buffer, said method comprising the steps of (a) connecting a bulk node of an output pullup transistor of said buffer to a pseudo-high-potential-power-rail, (b) connecting a first PMOS transistor between said output node and said pseudo-high-potential-power-rail, (c) connecting a second PMOS transistor between said pseudo-high-potential-power-rail and a gate node of said first PMOS transistor, (d) connecting a gate node of said second PMOS transistor to said output node, (e) coupling an NMOS linking transistor between said high-potential power rail and said pseudo-high-potential-power-rail, and coupling a gate node of said linking transistor to said high-potential power rail, (f) connecting a PMOS feedback transistor between said pseudo-high-potential-power-rail and a gate node of said output pullup transistor.
Claim 24
Dependent Claim
136 words
An output-buffer-power-rail-protecting method for guarding a high-potential power rail of an inactive-state output buffer against overvoltages on an output node of said buffer, said method comprising the steps of (a) connecting a bulk node of an output pullup transistor of said buffer to a pseudo-high-potential-power-rail, (b) connecting a first PMOS transistor between said output node and said pseudo-high-potential-power-rail, (c) connecting a second PMOS transistor between said pseudo-high-potential-power-rail and a gate node of said first PMOS transistor, (d) connecting a gate node of said second PMOS transistor to said output node, (e) coupling an NMOS linking transistor between said high-potential power rail and said pseudo-high-potential-power-rail, and coupling a gate node of said linking transistor to said high-potential power rail, (f) connecting a PMOS feedback transistor between said pseudo-high-potential-power-rail and a gate node of said output pullup transistor.
Claim 25
Dependent Claim
48 words
Method as described in claim 20 said method further comprising the steps of (a) interspersing an NMOS blocker transistor between a pullup-transistor driver transistor and said gate node of said pullup transistor and (b) connecting a gate node of said NMOS blocker transistor to said high-potential power rail.
Claim 26
Dependent Claim
48 words
Method as described in claim 21 said method further comprising the steps of (a) interspersing a second NMOS blocker transistor between a pullup-transistor-disabler transistor and said gate node of said pullup transistor and (b) connecting a gate node of said second NMOS blocker to said high-potential power rail.
Claim 27
Dependent Claim
136 words
An output-buffer-power-rail-protecting method for guarding a low-potential power rail of an inactive-state output buffer against undervoltages on an output node of said buffer, said method comprising the steps of (a) connecting a bulk node of an output pulldown transistor of said buffer to a pseudo-low-potential-power-rail, (b) connecting a first NMOS transistor between said output node and said pseudo-low-potential-power-rail, (c) connecting a second NMOS transistor between said pseudo-low-potential-power-rail and a gate node of said first NMOS transistor, (d) connecting a gate node of said second NMOS transistor to said output node, (e) coupling a PMOS linking transistor between said low-potential power rail and said pseudo-low-potential-power-rail, and coupling a gate node of said linking transistor to said low-potential power rail, (f) connecting an NMOS feedback transistor between said pseudo-low-potential-power-rail and a gate node of said output pulldown transistor.
Claim 28
Dependent Claim
136 words
An output-buffer-power-rail-protecting method for guarding a low-potential power rail of an inactive-state output buffer against undervoltages on an output node of said buffer, said method comprising the steps of (a) connecting a bulk node of an output pulldown transistor of said buffer to a pseudo-low-potential-power-rail, (b) connecting a first NMOS transistor between said output node and said pseudo-low-potential-power-rail, (c) connecting a second NMOS transistor between said pseudo-low-potential-power-rail and a gate node of said first NMOS transistor, (d) connecting a gate node of said second NMOS transistor to said output node, (e) coupling a PMOS linking transistor between said low-potential power rail and said pseudo-low-potential-power-rail, and coupling a gate node of said linking transistor to said low-potential power rail, (f) connecting an NMOS feedback transistor between said pseudo-low-potential-power-rail and a gate node of said output pulldown transistor.
Claim 29
Dependent Claim
48 words
Method as described in claim 23 said method further comprising the steps of (a) interspersing a PMOS blocker transistor between a pulldown-transistor driver transistor and said gate node of said pulldown transistor and (b) connecting a gate node of said PMOS blocker transistor to said low-potential power rail.
Claim 30
Dependent Claim
48 words
Method as described in claim 24 said method further comprising the steps of (a) interspersing a second PMOS blocker transistor between a pulldown-transistor-disabler transistor and said gate node of said pulldown transistor and (b) connecting a gate node of said second PMOS blocker to said low-potential power rail.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |