Cascadable peripheral data interface including a shift register, counter, and randomly-accessed registers of different bit length

Claim 1

A cascadable peripheral with an efficient data interface comprising: a data input terminal for receiving serial data synchronously with a clock signal when an enable signal is active; a shift register having a data input coupled to said data input terminal, a clock input for receiving said clock signal, a serial data output for providing data synchronously with said clock signal, and a parallel data output; a data output terminal coupled to said serial data output of said shift register, for coupling the cascadable peripheral to a second cascadable peripheral; a counter having a clock input for receiving said clock signal, a reset input for receiving a reset signal, and a multi-bit output indicative of a state of said counter, said counter counting a number of pulses of said clock signal received while said reset signal is inactive, said counter being reset in response to an activation of said reset signal; decoder means coupled to said counter, for providing a plurality of load signals each corresponding to one of a plurality of predetermined states, in response to said enable signal becoming inactive, and for providing said reset signal to said reset input of said counter; said decoder means activating said reset signal in response to either an inactivation of said enable signal or to a maximum count signal, said decoder means activating said maximum count signal in response to said state of said counter being equal to a size of said shift register; and a plurality of registers each having a load input receiving a corresponding one of said plurality of load signals and a multi-bit data input coupled to at least a part of said parallel data output of said shift register.

Claim 19

A method for efficient data interfacing in a cascadable peripheral, comprising the steps of: receiving a clock signal at an input of a counter during a time period in which an enable signal is active; receiving serial data at an input terminal of the cascadable peripheral synchronously with said clock signal; shifting said serial data through a shift register synchronously with said clock signal; providing data from a serial output of said shift register to an output terminal of the cascadable peripheral synchronously with said clock signal; resetting said counter in response to a state of said counter reaching a maximum count, said maximum count equal to a size of said shift register; decoding an output of said counter in response to said enable signal becoming inactive to activate one of a plurality of load signals; loading a selected register of a plurality of registers corresponding to said load signals, from a parallel output of said shift register.

Claim 20

A method for efficient data interfacing in a cascadable peripheral, comprising the steps of: receiving a clock signal at an input of a counter during a time period in which an enable signal is active; receiving serial data at an input terminal of the cascadable peripheral synchronously with said clock signal; shifting said serial data through a shift register synchronously with said clock signal; providing data from a serial output of said shift register to an output terminal of the cascadable peripheral synchronously with said clock signal; resetting said counter in response to a state of said counter reaching a maximum count, said maximum count equal to a size of said shift register; decoding an output of said counter in response to said enable signal becoming inactive to activate one of a plurality of load signals; loading a selected register of a plurality of registers corresponding to said load signals, from a parallel output of said shift register.