US5454095A
Expired / Lapsed
US
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Multi-processor system in which at least two processors access the same memory
Assignee: Robert Bosch GmbH
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Filing: 1994-04-05
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Granted: 1995-09-26
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Expires: 2014-04-05
Abstract
Abstract A multi-processor system that is useful for controlling processes of motor vehicles. The system having at least two processors that jointly access the same memory. The system memory is divided into at least two sectors. A first processor accesses one memory sector only in the read mode and a second processor accesses it only in the write mode. The second processor accesses the other memory sector only in the read mode and the first processor accesses it only in the write mode. The processors are synchronized in such a way that the processors access the memory in the same way at the same time.
Inventors
- 👤 Rolf Kraemer
- 👤 Herbert Graft
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:03
CPC Classifications
F; F02; F02D; F02D41/00; F02D41/24; F02D41/26; F02D41/266; G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/0421
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
141 words
A multi-processor system comprising: a memory, said memory including a first section and second section; and a first processor and a second processor each coupled with said memory such that said first processor can access said first memory section only in the read mode and said second memory section only in the write mode, and said second processor can access said first memory section only in the write mode and said second memory section only in the read mode, the second processor writing to the first memory section only when the first processor is writing to the second memory section, the second processor reading from the second memory section only when the first processor is reading from the first memory section, thereby preventing a concurrent access of either said first or second memory section by both said first and second processors.
Claim 2
Dependent Claim
141 words
A multi-processor system comprising: a memory, said memory including a first section and second section; and a first processor and a second processor each coupled with said memory such that said first processor can access said first memory section only in the read mode and said second memory section only in the write mode, and said second processor can access said first memory section only in the write mode and said second memory section only in the read mode, the second processor writing to the first memory section only when the first processor is writing to the second memory section, the second processor reading from the second memory section only when the first processor is reading from the first memory section, thereby preventing a concurrent access of either said first or second memory section by both said first and second processors.
Claim 3
Dependent Claim
26 words
The multi-processor system as recited in claim 1, wherein said first processor preforms read, write, and computing operations in an identical sequence as said second processor.
Claim 4
Dependent Claim
28 words
The multi-processor system as recited in claim 1, wherein said first and second processors first access said memory in the read mode and then in the write mode.
Claim 5
Dependent Claim
60 words
The multi-processor system as recited in claim 1, wherein said first processor is a master processor and is adapted to send an interrupt signal to said second processor, said second processor being a slave processor, said interrupt signal triggering said first and second processors to start a sequence of reading from said memory, writing to said memory, and compute operations.
Claim 6
Dependent Claim
37 words
The multi-processor system as recited in claim 4, wherein after said interrupt signal is sent, said first and second processors first access said memory in the read mode and then access said memory in the write mode.
Claim 7
Dependent Claim
78 words
The multi-processor system as recited in claim 4, further comprising a first transmission path between said master processor and an internal combustion engine and a second transmission path between said slave processor and said internal combustion engine, said master processor calculating and sending a fuel amount signal to said internal combustion engine via said first transmission path and said slave processor calculating and sending a start injection signal to said internal combustion engine via said second transmission path.
Claim 8
Dependent Claim
29 words
The multi-processor system as recited in claim 4, wherein said master processor calculates control signals and said slave processor calculates a fuel amount signal and a start injection signal.
Claim 9
Dependent Claim
78 words
The multi-processor system as recited in claim 1, further comprising a first transmission path between said first processor and an internal combustion engine and a second transmission path between said second processor and said internal combustion engine, said first processor calculating and sending a fuel amount signal to said internal combustion engine via said first transmission path and said second processor calculating and sending a start injection signal to said internal combustion engine via said second transmission path.
Claim 10
Dependent Claim
29 words
The multi-processor system as recited in claim 1, wherein said first processor calculates control signals and said second processor calculates a fuel amount signal and a start injection signal.
Claim 11
Dependent Claim
32 words
The multi-processor system as recited in claim 1, wherein said memory includes further memory sections, the further memory sections being used as an external RAM memory for said first and second processors.
Claim 12
Dependent Claim
110 words
A multi-processor system for controlling processes of a motor vehicle, comprising: N-1 memories each divided into N sections, where N is an integer >2; and N processors coupled with said N-1 memories such that each processor has direct or indirect access to each of the N-1 memories in a read mode and in a write mode, the N memory sections of any of the N-1 memories being accessed by only one of said N processors in the read or write mode at a given time, wherein operations of said N processors are synchronized such that said N processors access said N-1 memories in the same modes at the same time.
Claim 13
Dependent Claim
110 words
A multi-processor system for controlling processes of a motor vehicle, comprising: N-1 memories each divided into N sections, where N is an integer >2; and N processors coupled with said N-1 memories such that each processor has direct or indirect access to each of the N-1 memories in a read mode and in a write mode, the N memory sections of any of the N-1 memories being accessed by only one of said N processors in the read or write mode at a given time, wherein operations of said N processors are synchronized such that said N processors access said N-1 memories in the same modes at the same time.
Claim 14
Dependent Claim
22 words
The multi-processor system as recited in claim 11, wherein said N processors perform read, write and computing operations in an identical sequence.
Claim 15
Dependent Claim
51 words
The multi-processor system as recited in claim 12, wherein one of said N processors is a master processor and sends an interrupt signal to the other of said N processors, the other of said N processors are slave processors, wherein said interrupt triggers said N processors to start the identical sequence.
Claim 16
Dependent Claim
35 words
The multi-processor system as recited in claim 13, wherein after said interrupt signal triggers said N processors, said N processors first access said N-1 memories in the read mode and then in the write mode.
Claim 17
Dependent Claim
39 words
The multi-processor system as recited in claim 13, wherein said master processor calculates control signals, a slave processor calculates a fuel amount signal and a start injection signal, and another slave processor performs tasks associated data input and output.
Claim 18
Dependent Claim
27 words
The multi-processor system as recited in claim 11, wherein said N processors first access said N-1 memories in the read mode and then in the write mode.
Claim 19
Dependent Claim
48 words
The multi-processor system as recited in claim 11, wherein one of said N processors calculates control signals, and another of said N processors calculates a fuel amount signal and a start injection signal, and yet another of said N processors performs tasks associated with data input and output.
Claim 20
Dependent Claim
36 words
The multi-processor system as recited in claim 11, wherein at least one of said memory sections of said N-1 memories that exceed those necessary for data exchange is an external RAM memory for said N processors.
Claim 21
Independent Claim
165 words
A device comprising: a) a first processor; b) a second processor; c) a memory having a first section and a second section; d) a first one way data transmission link enabling said first processor to write data to said first section of said memory; e) a second one way data transmission link enabling said first processor to read data from said second section of said memory; f) a third one way data transmission link enabling said second processor to write data to said second section of said memory; g) a fourth one way data transmission link enabling said second processor to read data from said first section of said memory; h) said second processor reading data from said first section of said memory only when said first processor is reading data from said second section of said memory, said second processor writing data to said second section of said memory only when said first processor is writing data to said first section of said memory.
Claim 22
Independent Claim
165 words
A device comprising: a) a first processor; b) a second processor; c) a memory having a first section and a second section; d) a first one way data transmission link enabling said first processor to write data to said first section of said memory; e) a second one way data transmission link enabling said first processor to read data from said second section of said memory; f) a third one way data transmission link enabling said second processor to write data to said second section of said memory; g) a fourth one way data transmission link enabling said second processor to read data from said first section of said memory; h) said second processor reading data from said first section of said memory only when said first processor is reading data from said second section of said memory, said second processor writing data to said second section of said memory only when said first processor is writing data to said first section of said memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |