Patent US5454087A successfully refreshed from Google Patents.
US5454087A
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Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT
Assignee: Advanced Processor Technologies LLC
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Filing: 1992-10-23
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Granted: 1995-09-26
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Expires: 2012-10-23
Abstract
Abstract An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.
Inventors
- 👤 Susumu Narita
- 👤 Fumio Arakawa
- 👤 Kunio Uchiyama
- 👤 Hirokazu Aoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 00:54
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3005; G06F9/30054; G06F9/32; G06F9/322; G06F9/323; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3806; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4486
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
303 words
A data processor comprising: a prefetch address generator for generating a prefetch address; a prefetch queue for prefetching an instruction from a memory according to the prefetch address and storing the instruction; an instruction decoder for decoding the instruction stored in said prefetch queue; an arithmetic logic unit(ALU), controlled by an output from said instruction decoder, for generating a branch target address of a branch instruction in accordance with an address calculation; a first buffer having a plurality of entries each of which is for storing therein an address of the branch instruction input from said prefetch address generator, the branch target address of the branch instruction input from said ALU, and information input from said instruction decoder indicating a type of the branch instruction; a second buffer having a plurality of entries each of which is for storing therein a return address, input from said ALU, for a return from a subroutine to a main processing routine; and a comparator for comparing the prefetch address with branch instruction addresses stored in said first buffer, wherein: when matching between the prefetch address and the branch instruction address is detected by said comparator, if the type information read from said first buffer indicates that the instruction for which the matching is detected is a branch instruction rather than a return instruction for the return from the subroutine to the main processing routine, the branch target address is read from said first buffer; and when the matching between the prefetch address and the branch instruction address is detected by said comparator, if the type information read from said first buffer indicates that the instruction for which the matching is detected is a return instruction for a return from a subroutine to the main processing routine, the return address is always read from said second buffer.
Claim 2
Dependent Claim
303 words
A data processor comprising: a prefetch address generator for generating a prefetch address; a prefetch queue for prefetching an instruction from a memory according to the prefetch address and storing the instruction; an instruction decoder for decoding the instruction stored in said prefetch queue; an arithmetic logic unit(ALU), controlled by an output from said instruction decoder, for generating a branch target address of a branch instruction in accordance with an address calculation; a first buffer having a plurality of entries each of which is for storing therein an address of the branch instruction input from said prefetch address generator, the branch target address of the branch instruction input from said ALU, and information input from said instruction decoder indicating a type of the branch instruction; a second buffer having a plurality of entries each of which is for storing therein a return address, input from said ALU, for a return from a subroutine to a main processing routine; and a comparator for comparing the prefetch address with branch instruction addresses stored in said first buffer, wherein: when matching between the prefetch address and the branch instruction address is detected by said comparator, if the type information read from said first buffer indicates that the instruction for which the matching is detected is a branch instruction rather than a return instruction for the return from the subroutine to the main processing routine, the branch target address is read from said first buffer; and when the matching between the prefetch address and the branch instruction address is detected by said comparator, if the type information read from said first buffer indicates that the instruction for which the matching is detected is a return instruction for a return from a subroutine to the main processing routine, the return address is always read from said second buffer.
Claim 3
Dependent Claim
41 words
A data processor according to claim 1, wherein said memory is a cache memory in which the instruction is stored from an external memory, the instruction being prefetched from said cache memory to said prefetch queue according to the prefetch address.
Claim 4
Dependent Claim
39 words
A data processor according to claim 2, wherein said prefetch queue, said instruction decoder, said arithmetic logic unit, said comparator, said first buffer, said second buffer and said cache memory are formed on a semiconductor chip of a microprocessor.
Claim 5
Dependent Claim
23 words
A data processor according to claim 3, wherein said prefetch queue, said instruction decoder, and said arithmetic logic unit conduct a pipeline operation.
Claim 6
Dependent Claim
16 words
A data processor according to claim 4, wherein said second buffer is a last-in first-out buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |