US5453719A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Oscillator circuit generating oscillation signal responsive to one of resonant element and external clock signal
Assignee: Renesas Electronics Corp
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Filing: 1994-11-07
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Granted: 1995-09-26
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Expires: 2014-11-07
Abstract
Abstract Disclosed herein is an oscillator circuit generating an oscillation signal in response to a resonant element in a first mode and to an external clock signal in a second mode. This oscillator circuit comprises a tri-state inverter circuit and a transfer circuit between the input and output nodes of the tri-state inverter circuit, and the output node of the tri-state inverter circuit is brought into a high impedance condition when an external clock signal is used and into an active state when the resonant element is employed.
Inventors
- 👤 Tetsuya Narahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:47
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/30; H03B5/32; H03B5/36; H03B5/364; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/354; H03K3/3545
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
152 words
An oscillator circuit comprising a first terminal, a second terminal, a tri-state inverter circuit having an input node coupled to said first terminal, and an output node coupled to said second terminal, a feedback circuit coupled between said first and second terminals, a detection circuit coupled to said second terminal for detecting whether said second terminal is connected with a resonant element or said second terminal receives a clock signal, and for producing a detection signal, said detection signal taking a first level when said second terminal is connected with said resonant element and a second level when said second terminal receives said clock signal, and a control circuit activating each of said tri-state inverter circuit and said feedback circuit in response to said first level of said detection signal and deactivating each of said tri-state inverter circuit and said feedback circuit in response to said second level of said detection signal.
Claim 2
Dependent Claim
152 words
An oscillator circuit comprising a first terminal, a second terminal, a tri-state inverter circuit having an input node coupled to said first terminal, and an output node coupled to said second terminal, a feedback circuit coupled between said first and second terminals, a detection circuit coupled to said second terminal for detecting whether said second terminal is connected with a resonant element or said second terminal receives a clock signal, and for producing a detection signal, said detection signal taking a first level when said second terminal is connected with said resonant element and a second level when said second terminal receives said clock signal, and a control circuit activating each of said tri-state inverter circuit and said feedback circuit in response to said first level of said detection signal and deactivating each of said tri-state inverter circuit and said feedback circuit in response to said second level of said detection signal.
Claim 3
Dependent Claim
63 words
The circuit as claimed in claim 1, wherein said detection circuit includes a capacitor, means responsive to said second terminal being connected to said resonant element for discharging said capacitor to produce said detection signal taking said first level, and means responsive to said second terminal receiving said clock signal for charging said capacitor to produce said detection signal taking said second level.
Claim 4
Dependent Claim
63 words
The circuit as claimed in claim 2, wherein said detection circuit further includes a bi-stable circuit which is brought into a first state by discharging said capacitor and into a second state by charging said capacitor, said detection signal taking said first level by said first state of said bi-stable circuit and said second level by said second state of said bi-stable circuit.
Claim 5
Dependent Claim
35 words
The circuit as claimed in claim 1, wherein said detection circuit including a counter counting changes in level at said second terminal to produce said detection signal taking one of said first and second levels.
References Cited (Backward Citations)
GB2005944A
Cited
US4551634A
Cited
JPS62186617A
Cited
US5101127A
Cited
US4896122A
Cited
US5196810A
Cited
US5036215A
Cited
JPH03274810A
Cited
US5140197A
Cited
US5151613A
Cited
JPH0575342A
Cited
US5136185A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |