Semiconductor read only memory

Claim 2

A semiconductor read only memory comprising: a memory cell array including a plurality of memory cell groups, said plurality of memory cell groups each including a plurality of memory cells; select means for selecting an arbitrary memory cell group from among said plurality of memory cell groups in response to an address input signal; address storage means for storing address information of a defective memory cell, the address storage means receiving an address input signal and outputting a group address signal of a memory cell group including the detective memory cell when the address input signal includes address information of the defective memory cell: data storage means for storing a plurality of data to be written into the memory cell group including the detective memory cell, the data storage means receiving the address input signal and the group address signal and reproducing one of the plurality of data in response to the address input signal and the group address signal; and bit identification storage means for storing bit line information of a defective memory cell, the bit identification storage means receiving the group address signal and outputting a sense amplifier bit signal in response to the group address signal; wherein the sense amplifier bit signal includes an information of a sense amplifier bit which is a sense amplifier receive defective group to be read out from the plurality of memory cell.

Claim 3

A semiconductor read only memory according to claim 1, wherein the semiconductor read only memory further includes switch means for receiving data of the memory cell, the one of the plurality of data and the sense amplifier bit signal, and the switch means masking the data of the memory cell in accordance with the sense amplifier bit signal.

Claim 4

A semiconductor read only memory comprising: a memory cell array including a plurality of memory cell banks, said memory cell array comprising a plurality of first lines and a plurality of second lines, said plurality of memory cell banks each including a plurality of memory cell MOS transistors provided between two adjacent first lines, portions of the respective two adjacent first lines forming source/drain regions of said plurality of MOS transistors; select means for selecting an arbitrary memory cell bank from among said plurality of memory cell banks by interconnecting the first lines to the second lines; address storage means for storing address information of a defective memory cell, the address storage means receiving an address input signal and outputting a bank address signal of a memory cell bank including the defective memory cell when the address input signal includes address information of the defective memory cell; data storage means for storing a plurality of data to be written into the memory cell bank including the defective memory cell, the data storage means receiving the address input signal and the bank address signal and reproducing one of the plurality of data in response to the address input signal and the bank address signal; and bit identification storage means for storing bit line information of a defective memory cell, the bit identification storage means receiving the bank address signal and outputting a sense amplifier bit signal in response to the bank address signal.

Claim 5

A semiconductor read only memory comprising: a memory cell array including a plurality of memory cell banks, said memory cell array comprising a plurality of first lines and a plurality of second lines, said plurality of memory cell banks each including a plurality of memory cell MOS transistors provided between two adjacent first lines, portions of the respective two adjacent first lines forming source/drain regions of said plurality of MOS transistors; select means for selecting an arbitrary memory cell bank from among said plurality of memory cell banks by interconnecting the first lines to the second lines; address storage means for storing address information of a defective memory cell, the address storage means receiving an address input signal and outputting a bank address signal of a memory cell bank including the defective memory cell when the address input signal includes address information of the defective memory cell; data storage means for storing a plurality of data to be written into the memory cell bank including the defective memory cell, the data storage means receiving the address input signal and the bank address signal and reproducing one of the plurality of data in response to the address input signal and the bank address signal; and bit identification storage means for storing bit line information of a defective memory cell, the bit identification storage means receiving the bank address signal and outputting a sense amplifier bit signal in response to the bank address signal.

Claim 6

A semiconductor read only memory according to claim 3, wherein the address storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the address information in accordance with the conductive or non-conductive state of each fuse element.

Claim 7

A semiconductor read only memory according to claim 3, wherein the data storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the plurality of data in accordance with the conductive or non-conductive state of each fuse element.

Claim 8

A semiconductor read only memory according to claim 3, wherein the address storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the address information in accordance with the conductive or non-conductive state of each fuse element; and the data storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the plurality of data in accordance with the conductive or non-conductive state of each fuse element.

Claim 9

A semiconductor read only memory according to claim 3, wherein the semiconductor read only memory further includes switch means for receiving data of the memory cell, the one of the plurality of data and the sense amplifier bit signal, and the switch means masking the data of the memory cell in accordance with the sense amplifier bit signal.

Claim 10

A semiconductor read only memory comprising: a memory cell array including a plurality of memory cell banks, each of said plurality of memory cell banks comprising a memory cell column constituted by a plurality of memory cells connected in series and a plurality of bit lines connected to the memory cell column; and select means for selecting an arbitrary memory cell bank among said plurality of memory cell banks by interconnecting the bit line to the memory cell column; address storage means for storing address information of a defective memory cell, the address storage means receiving an address input signal and outputting a bank address signal of a memory cell bank including the defective memory cell when the address input signal includes address information of the defective memory cell; data storage means for storing a plurality of data to be written into the memory cell bank including the defective memory cell, the data storage means receiving the address input signal and the bank address signal and reproducing one of the plurality of data in response to the address input signal and the bank address signal; and bit identification storage means for storing bit line information of a defective memory cell, the bit identification storage means receiving the bank address signal and outputting a sense amplifier bit signal in response to the bank address signal.

Claim 11

A semiconductor read only memory comprising: a memory cell array including a plurality of memory cell banks, each of said plurality of memory cell banks comprising a memory cell column constituted by a plurality of memory cells connected in series and a plurality of bit lines connected to the memory cell column; and select means for selecting an arbitrary memory cell bank among said plurality of memory cell banks by interconnecting the bit line to the memory cell column; address storage means for storing address information of a defective memory cell, the address storage means receiving an address input signal and outputting a bank address signal of a memory cell bank including the defective memory cell when the address input signal includes address information of the defective memory cell; data storage means for storing a plurality of data to be written into the memory cell bank including the defective memory cell, the data storage means receiving the address input signal and the bank address signal and reproducing one of the plurality of data in response to the address input signal and the bank address signal; and bit identification storage means for storing bit line information of a defective memory cell, the bit identification storage means receiving the bank address signal and outputting a sense amplifier bit signal in response to the bank address signal.

Claim 12

A semiconductor read only memory according to claim 8, wherein the address storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the address information in accordance with the conductive or non-conductive state of each fuse element.

Claim 13

A semiconductor read only memory according to claim 8, wherein the data storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the plurality of data in accordance with the conductive or non-conductive state of each fuse element.

Claim 14

A semiconductor read only memory according to claim 8, wherein the address storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the address information in accordance with the conductive or non-conductive state of each fuse element; and the data storage means has a plurality of fuse elements to be disconnected by laser light or electrical means, and stores the plurality of data in accordance with the conductive or non-conductive state of each fuse element.

Claim 15

A semiconductor read only memory according to claim 8, wherein the semiconductor read only memory further includes switch means for receiving data of the memory cell, the one of the plurality of data and the sense amplifier bit signal, and the switch means masking the data of the memory cell in accordance with the sense amplifier bit signal.