US5452254A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Renesas Electronics Corp
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Filing: 1994-09-29
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Granted: 1995-09-19
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Expires: 2014-09-29
Abstract
Abstract In a semiconductor memory circuit, when a memory cell is not selected, a pair of complementary data lines connected to the memory cell are short-circuited to be brought to the same potential, and when the memory cell is selected, the short-circuiting is cancelled. Therefore, the complementary data lines are in no way put in a floating condition, and when the memory cell is selected, a voltage difference corresponding to the data to be read out is immediately generated between the complementary data lines. Accordingly, the data is quickly fixed or settled, without being influenced by a preceding read-out data.
Inventors
- 👤 Hiroyuki Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
210 words
A semiconductor memory device comprising; a pair of complementary data lines for outputting a content of a memory cell in the form of a pair of differential signals; amplifying means for detecting and amplifying said pair of differential signals; enable means for selectively enabling and disabling said amplifying means; floating means for maintaining said pair of complementary data lines in a floating condition when said amplifying means is put in a disabled condition by said enable means; and short-circuit means for short-circuiting said pair of complementary data lines when said amplifying means is put in said disabled condition, wherein said short-circuit means short-circuits said pair of complementary data lines in synchronism with an enable signal for putting said amplifying means into the disabled condition, wherein said amplifying means includes a differential circuit comprising a pair of bipolar transistors having their base connected to said pair of complementary data lines, respectively, and wherein said enable means includes level converting means for receiving said enable signal and for converting a level of said enable signal, and further includes delay means for receiving said enable signal to delay said enable signal in correspondence to a delay time occurring in said level converting means, the delayed enable signal being supplied to said short-circuit means.
Claim 2
Dependent Claim
210 words
A semiconductor memory device comprising; a pair of complementary data lines for outputting a content of a memory cell in the form of a pair of differential signals; amplifying means for detecting and amplifying said pair of differential signals; enable means for selectively enabling and disabling said amplifying means; floating means for maintaining said pair of complementary data lines in a floating condition when said amplifying means is put in a disabled condition by said enable means; and short-circuit means for short-circuiting said pair of complementary data lines when said amplifying means is put in said disabled condition, wherein said short-circuit means short-circuits said pair of complementary data lines in synchronism with an enable signal for putting said amplifying means into the disabled condition, wherein said amplifying means includes a differential circuit comprising a pair of bipolar transistors having their base connected to said pair of complementary data lines, respectively, and wherein said enable means includes level converting means for receiving said enable signal and for converting a level of said enable signal, and further includes delay means for receiving said enable signal to delay said enable signal in correspondence to a delay time occurring in said level converting means, the delayed enable signal being supplied to said short-circuit means.
Claim 3
Dependent Claim
60 words
A semiconductor memory device claimed in claim 1 wherein said floating means includes a pair of emitter follower transistors having their base connected to receive said pair of differential signals read from said memory cell, respectively, and a pair of current sources connected to an emitter of said emitter follower transistors and on-off controlled in response to said enable signal.
Claim 4
Dependent Claim
29 words
A semiconductor memory device claimed in claim 2 wherein said pair of complementary data lines are connected through a wired-OR to a plurality of pairs of emitter follower transistors.
Claim 5
Dependent Claim
49 words
A semiconductor memory device claimed in claim 3 further including a short-circuit canceling means for canceling the short-circuiting between said pair of complementary data lines after a potential on said pair of complementary data lines changes in accordance with said pair of differential signals read from said memory cell.
Claim 6
Dependent Claim
26 words
A semiconductor memory device claimed in claim 2, wherein said short-circuit means is also for setting said pair of complementary data lines to a predetermined voltage.
Claim 7
Dependent Claim
34 words
A semiconductor memory device claimed in claim 5 wherein said predetermined voltage is a voltage near to an emitter bias voltage of said emitter follower transistors when said emitter follower transistors are in operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |