Patent US3483347A successfully refreshed from Google Patents.
Patent US5452239A successfully refreshed from Google Patents.
US5452239A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
Assignee: Cadence Design Systems Inc
•
Filing: 1993-02-26
•
Granted: 1995-09-19
•
Expires: 2013-02-26
Abstract
Abstract An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.
Inventors
- 👤 Wei-Jin Dai
- 👤 Louis Galbiati, III
- 👤 Joseph Varghese
- 👤 Dam V. Bui
- 👤 Stephen P. Sample
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:43
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F30/327; G06F30/34; G06F30/347; G06F2117/00; G06F2117/04; G06F2119/00; G06F2119/12
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
235 words
In a hardware emulation system, a method of removing gated clocks from clock nets in a circuit design comprising the steps of: (a) identifying the clock nets in the netlist; (b) identifying clock sources, said clock sources being unique clock signals in the clock nets; (c) identifying sites where logic in the clock net is connected to a clock pin on a flip-flop; (d) determining whether pre-existing logic is connected to a clock enable pin on said flip-flop; (e) determining whether said logic in the clock net is clock-gating logic or clock generation logic; (f) transforming said logic in the clock net into functional equivalent logic if said clock net logic is clock-gating logic; (g) connecting said functional equivalent logic to said clock enable pin on said flip-flop if there is no pre-existing logic connected to said clock enable pin; (h) creating an AND gate having an output and a first input and a second input and connecting said output of said AND gate to said clock enable pin of said flip-flop, connecting said functional equivalent logic to said first input on said AND gate and transferring said pre-existing logic to said second input on said AND gate, if pre-existing logic is connected to said clock enable; (i) connecting said clock sources to said clock pin on said flip-flop, thereby creating a modified netlist; and (j) mapping said modified netlist into said hardware emulation system.
Claim 2
Dependent Claim
235 words
In a hardware emulation system, a method of removing gated clocks from clock nets in a circuit design comprising the steps of: (a) identifying the clock nets in the netlist; (b) identifying clock sources, said clock sources being unique clock signals in the clock nets; (c) identifying sites where logic in the clock net is connected to a clock pin on a flip-flop; (d) determining whether pre-existing logic is connected to a clock enable pin on said flip-flop; (e) determining whether said logic in the clock net is clock-gating logic or clock generation logic; (f) transforming said logic in the clock net into functional equivalent logic if said clock net logic is clock-gating logic; (g) connecting said functional equivalent logic to said clock enable pin on said flip-flop if there is no pre-existing logic connected to said clock enable pin; (h) creating an AND gate having an output and a first input and a second input and connecting said output of said AND gate to said clock enable pin of said flip-flop, connecting said functional equivalent logic to said first input on said AND gate and transferring said pre-existing logic to said second input on said AND gate, if pre-existing logic is connected to said clock enable; (i) connecting said clock sources to said clock pin on said flip-flop, thereby creating a modified netlist; and (j) mapping said modified netlist into said hardware emulation system.
Claim 3
Dependent Claim
95 words
The method of claim 1 further comprising the steps of: (a) determining if any of said clock nets that were transformed have logic emanating from a branch point in said clock path leading to clock source and said branch leads to a data path; (b) determining if any of said clock nets that could not be transformed have logic emanating from a branch point; and (c) duplicating said logic in said clock path from said branch point to said source clock if either of the conditions to be determined in steps (a) or (b) exist.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |