Patent US5452235A successfully refreshed from Google Patents.
US5452235A
Expired / Lapsed
US
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Planar/packed video data FIFO memory device
Assignee: Intel Corp
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Filing: 1993-11-01
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Granted: 1995-09-19
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Expires: 2013-11-01
Abstract
Abstract A memory device for a digital video system, capable of receiving video data in a packed format and transmitting that video data in a planar format. In other operating modes, the memory device receives video data in various packed formats and transmits that video data in a packed format. The memory device is suitable for a flexible digital video system in which video data may either be displayed in real time as it is generated (using packed format data) or compressed for storage and future display (using planar format data).
Inventors
- 👤 Tarik Isani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:04
CPC Classifications
H; H04; H04N; H04N11/00; H04N11/06; H04N11/20; H04N11/04; H04N11/042; H04N5/00; H04N5/76; H04N5/907
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
291 words
A memory device for receiving video data in a packed format and for selectively converting the video data to a planar format, comprising: (a) a video scaler; (b) a pixel router, electrically connected to receive the video data from the video scaler; (c) a first first-in, first-out memory device (FIFO), electrically connected to receive a first subset of the video data from a first portion of the pixel router; (d) a second FIFO, electrically connected to receive a second subset of the video data from a second portion of the pixel router; (e) a third FIFO, electrically connected to receive a third subset of the video data from a third portion of the pixel router; and (f) a data multiplexer, electrically connected to receive the video data from the first, second, and third FIFOs, wherein: the video scaler receives the video data and selectively transmits the video data to the first, second, and third portions of the pixel router; the first, second, and third portions of the pixel router transmit the first, second, and third subsets of the video data to the first, second, and third FIFOs, respectively; the data multiplexer selectively receives the first, second, and third subsets of the video data from the first, second, and third FIFOs, respectively, for further transmission; the memory device has a planar mode for receiving the video data in a first packed format and transmitting the video data in a first planar format; the memory device has a packed mode for receiving the video data in a second packed format and transmitting the video data in the second packed format; and the first, second, and third FIFOs are used to store the video data in both the planar mode and the packed mode.
Claim 2
Dependent Claim
291 words
A memory device for receiving video data in a packed format and for selectively converting the video data to a planar format, comprising: (a) a video scaler; (b) a pixel router, electrically connected to receive the video data from the video scaler; (c) a first first-in, first-out memory device (FIFO), electrically connected to receive a first subset of the video data from a first portion of the pixel router; (d) a second FIFO, electrically connected to receive a second subset of the video data from a second portion of the pixel router; (e) a third FIFO, electrically connected to receive a third subset of the video data from a third portion of the pixel router; and (f) a data multiplexer, electrically connected to receive the video data from the first, second, and third FIFOs, wherein: the video scaler receives the video data and selectively transmits the video data to the first, second, and third portions of the pixel router; the first, second, and third portions of the pixel router transmit the first, second, and third subsets of the video data to the first, second, and third FIFOs, respectively; the data multiplexer selectively receives the first, second, and third subsets of the video data from the first, second, and third FIFOs, respectively, for further transmission; the memory device has a planar mode for receiving the video data in a first packed format and transmitting the video data in a first planar format; the memory device has a packed mode for receiving the video data in a second packed format and transmitting the video data in the second packed format; and the first, second, and third FIFOs are used to store the video data in both the planar mode and the packed mode.
Claim 3
Dependent Claim
45 words
The memory device of claim 1, wherein: the depth of the second FIFO is equal to the depth of the third FIFO; and the depth of the first FIFO is 2 n times the depth of the second FIFO, wherein n is a non-negative integer.
Claim 4
Dependent Claim
22 words
The memory device of claim 2, wherein the depth of the first FIFO is two times the depth of the second FIFO.
Claim 5
Dependent Claim
42 words
The memory device of claim 1, wherein: the first packed format is one of YUV16 packed format, YUV12 packed format, and YUV9 packed format; and the second packed format is one of RGB24 packed format, RGB16 packed format, and YUV16 packed format.
Claim 6
Dependent Claim
96 words
The memory device of claim 1, wherein: when operated in the planar mode, the memory device receives the video data in the first packed format from a video capture source and the memory device transmits the video data in the first planar format for receipt and compression by a data compressor; and when operated in the packed mode, the memory device receives the video data in the second packed format from the video capture source and the memory device transmits the video data in the second packed format for receipt and display by a graphic display.
Claim 7
Dependent Claim
59 words
The memory device of claim 1, wherein: the first portion of the pixel router comprises four 8-bit registers; the second portion of the pixel router comprises four 8-bit registers; the third portion of the pixel router comprises four 8-bit registers; the first FIFO comprises 32-bit registers; the second FIFO comprises 32-bit registers; and the third FIFO comprises 32-bit registers.
Claim 8
Dependent Claim
160 words
The memory device of claim 6, wherein: the depth of the second FIFO is equal to the depth of the third FIFO; the depth of the first FIFO is two times the depth of the second FIFO; the first packed format is one of YUV16 packed format, YUV12 packed format, and YUV9 packed format; the second packed format is one of RGB24 packed format, RGB16 packed format, and YUV16 packed format; when operated in the planar mode, the memory device receives the video data in the first packed format from a video capture source and the memory device transmits the video data in the first planar format for receipt and compression by a data compressor; and when operated in the packed mode, the memory device receives the video data in the second packed format from the video capture source and the memory device transmits the video data in the second packed format for receipt and display by a graphic display.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |