Programmable duty cycle converter

Claim 2

A duty cycle converter comprising: an input for receiving an input pulsed signal including a plurality of input pulses having a leading edge and a trailing edge and exhibiting a first duty cycle; an output pulse generator for generating an output pulse in response to each input pulse, each output pulse including a leading edge and a trailing edge, each output pulse being provided to an output of the output pulse generator, the output pulse generator including synchronizing means for synchronizing the leading edges of the output pulses with the leading edges of respective input pulses; timing means, coupled to the output pulse generator, for controlling the timing of the trailing edges of the output pulses, the timing means including first and second capacitors; a current source, switchably coupled to the first capacitor, the current source charging the first capacitor to a first voltage level in response to a first input pulse; a third capacitor, switchably coupled to the first capacitor, for discharging the first capacitor to a second voltage level in response to a second input pulse; the current source being switchably coupled to the second capacitor for charging the second capacitor in response to the second input pulse; and a comparator, coupled to the first and second capacitors, for determining when the voltage on the second capacitor becomes equal to the second voltage level on the first capacitor and in response generating a transition in a comparator output signal; the output pulse generator being coupled to the comparator such that when a first output pulse is generated by the output pulse generator in response to the first input pulse, the transition in the comparator output signal causes the first output pulse to be terminated such that the trailing edge of the first output pulse occurs upon such transition.

Claim 3

The duty cycle converter of claim 1 wherein the output pulse generator comprises an RS flip flop.

Claim 4

The duty cycle converter of claim 1 wherein the capacitance of the first capacitor is equal to the capacitance of the second capacitor.

Claim 5

The duty cycle converter of claim 3 wherein the capacitance of the third capacitor is equal to the capacitance of the first capacitor.

Claim 6

The duty cycle converter of claim 3 wherein the capacitance of the third capacitor is greater than the capacitance of the first capacitor.

Claim 7

The duty cycle converter of claim 3 wherein the capacitance of the third capacitor is less than the capacitance of the first capacitor.

Claim 8

A duty cycle converter comprising: an input for receiving an input pulsed signal including a plurality of input pulses having a leading edge and a trailing edge and exhibiting a first duty cycle; an output pulse generator for generating an output pulse in response to each input pulse, each output pulse including a leading edge and a trailing edge, each output pulse being provided to an output of the output pulse generator, the output pulse generator including synchronizing means for synchronizing the leading edges of the output pulses with the leading edges of respective input pulses; timing means, coupled to the output pulse generator, for controlling the timing of the trailing edges of the output pulses; the timing means including first and second capacitors; a current source, switchably coupled to the first capacitor, the current source charging the first capacitor to a first voltage level in response to a first input pulse; a third capacitor, switchably coupled to the first capacitor, for discharging the first capacitor to a second voltage level in response to a second input pulse; the current source being switchably coupled to the second capacitor for charging the second capacitor in response to the second input pulse; resetting means, coupled to the first capacitor, for resetting the voltage on the first capacitor to zero prior to a third input pulse; a fourth capacitor, switchably coupled to the second capacitor, for discharging the second capacitor to the second voltage level in response to the third input pulse; the current source being switchably coupled to the first capacitor for charging the first capacitor in response to the third input pulse; and a comparator, coupled to the first and second capacitors, for generating a comparator output signal which exhibits a transition each time that the voltage on the second capacitor increases to equal the voltage on the first capacitor and each time that the voltage on the first capacitor increases to equal the voltage on the second capacitor; the output pulse generator being coupled to the comparator such that each output pulse is terminated when a respective transition in the comparator output signal occurs thus providing an output pulsed signal exhibiting a second duty cycle.

Claim 9

A duty cycle converter comprising: an input for receiving an input pulsed signal including a plurality of input pulses having a leading edge and a trailing edge and exhibiting a first duty cycle; an output pulse generator for generating an output pulse in response to each input pulse, each output pulse including a leading edge and a trailing edge, each output pulse being provided to an output of the output pulse generator, the output pulse generator including synchronizing means for synchronizing the leading edges of the output pulses with the leading edges of respective input pulses; timing means, coupled to the output pulse generator, for controlling the timing of the trailing edges of the output pulses; the timing means including first and second capacitors; a current source, switchably coupled to the first capacitor, the current source charging the first capacitor to a first voltage level in response to a first input pulse; a third capacitor, switchably coupled to the first capacitor, for discharging the first capacitor to a second voltage level in response to a second input pulse; the current source being switchably coupled to the second capacitor for charging the second capacitor in response to the second input pulse; resetting means, coupled to the first capacitor, for resetting the voltage on the first capacitor to zero prior to a third input pulse; a fourth capacitor, switchably coupled to the second capacitor, for discharging the second capacitor to the second voltage level in response to the third input pulse; the current source being switchably coupled to the first capacitor for charging the first capacitor in response to the third input pulse; and a comparator, coupled to the first and second capacitors, for generating a comparator output signal which exhibits a transition each time that the voltage on the second capacitor increases to equal the voltage on the first capacitor and each time that the voltage on the first capacitor increases to equal the voltage on the second capacitor; the output pulse generator being coupled to the comparator such that each output pulse is terminated when a respective transition in the comparator output signal occurs thus providing an output pulsed signal exhibiting a second duty cycle.

Claim 10

The duty cycle converter of claim 7 wherein the output pulse generator comprises an RS flip flop.

Claim 11

The duty cycle converter of claim 7 wherein the capacitance of the first capacitor is equal to the capacitance of the second capacitor.

Claim 12

The duty cycle converter of claim 9 wherein the capacitance of the third capacitor is equal to the capacitance of the first capacitor.

Claim 13

The duty cycle converter of claim 9 wherein the capacitance of the third capacitor is greater than the capacitance of the first capacitor.

Claim 14

The duty cycle converter of claim 9 wherein the capacitance of the third capacitor is less than the capacitance of the first capacitor.

Claim 15

The duty cycle converter of claim 7 wherein the first and second capacitors comprise variable capacitors.

Claim 16

The duty cycle converter of claim 13 further comprising a selector, coupled to the first and second capacitors, for selecting the capacitance value of the first and second capacitors to determine the duty cycle exhibited by the output signal.