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US5451810A
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Metal-to-metal antifuse structure
Assignee: Texas Instruments Inc
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Filing: 1993-12-14
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Granted: 1995-09-19
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Expires: 2013-12-14
Abstract
Abstract A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon layer 28. An antifuse via 44 is etched through an interlevel dielectric layer 36 to the antifuse stack 32. Next, a portion of the etchstop layer at the bottom of via 44 is removed. Finally, a second layer of metal 48 is deposited to fill antifuse via 44 and etched to form the desired interconnections.
Inventors
- 👤 Howard L. Tigelaar
- 👤 George Misium
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10W20/40; H10W20/49; H10W20/491; Y; Y10; Y10S; Y10S148/00; Y10S148/055
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
119 words
A metal-to-metal antifuse structure located on a semiconductor device comprising. a. an antifuse stack located on said semiconductor device comprising: i. a bottom plate comprising conductive material adjacent said semiconductor device; ii. an antifuse dielectric comprising amorphous silicon located on said bottom plate; and iii. an etchstop layer located above said antifuse dielectric; b. an interlevel dielectric located above said semiconductor device and said antifuse stack; c. at least one via extending through said interlevel dielectric and said etchstop layer to said antifuse dielectric; and d. a top plate comprising conductive material and located adjacent said antifuse dielectric in said at least one via, wherein an electrical size of said metal-to-metal antifuse structure is determined by said top plate.
Claim 2
Dependent Claim
119 words
A metal-to-metal antifuse structure located on a semiconductor device comprising. a. an antifuse stack located on said semiconductor device comprising: i. a bottom plate comprising conductive material adjacent said semiconductor device; ii. an antifuse dielectric comprising amorphous silicon located on said bottom plate; and iii. an etchstop layer located above said antifuse dielectric; b. an interlevel dielectric located above said semiconductor device and said antifuse stack; c. at least one via extending through said interlevel dielectric and said etchstop layer to said antifuse dielectric; and d. a top plate comprising conductive material and located adjacent said antifuse dielectric in said at least one via, wherein an electrical size of said metal-to-metal antifuse structure is determined by said top plate.
Claim 3
Dependent Claim
15 words
The structure of claim 1 wherein said bottom plate and said top plate comprise TiW.
Claim 4
Dependent Claim
15 words
The structure of claim 1 wherein said bottom plate and said top plate comprise TiN.
Claim 5
Dependent Claim
11 words
The structure of claim 1 wherein said etchstop layer comprises aluminum.
Claim 6
Dependent Claim
11 words
The structure of claim 1 wherein said etchstop layer comprises aluminum-oxide.
Claim 7
Dependent Claim
28 words
The structure of claim 1 wherein said etchstop layer comprises a layer of oxide adjacent said dielectric layer and a layer of amorphous silicon overlying said oxide layer.
Claim 8
Dependent Claim
15 words
The structure of claim 1 wherein said bottom plate and said top plate comprise titanium.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |