Patent US5451807A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5451807A Expired / Lapsed US ⏱️ 0.0 years remaining

Metal oxide semiconductor field effect transistor

Assignee: Mitsubishi Electric Corp
•
Filing: 1994-04-20
•
Granted: 1995-09-19
•
Expires: 2014-04-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A field effect transistor includes a gate electrode disposed on a first conductivity type semiconductor substrate via an insulating film, a second conductivity type region having a first dopant impurity concentration region in the substrate at the drain side of the gate electrode contacting the insulating film, a second conductivity type region in the substrate having a higher dopant impurity concentration than the first dopant impurity concentration at the source side of the gate electrode contacting the insulating film, and a first conductivity type region in the substrate having a higher dopant impurity concentration than the substrate and surrounding the source region in the substrate. The ON-resistance of the transistor is reduced. The first conductivity type region improves the drain-source breakdown voltage, suppresses variations in the threshold voltage, and reduces the gate-source and gate-drain capacitances.

Inventors

  • 👤 Koichi Fujita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 17:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D62/351; H10D62/357; H10D62/364; H10D62/371

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 245 words
A metal oxide semiconductor field effect transistor comprising: a first conductivity type semiconductor substrate having a surface and a first dopant impurity concentration; an insulating film disposed on the surface of said substrate; a gate electrode disposed on said insulating film at a region of said first conductivity type semiconductor substrate; source and drain regions having a second dopant impurity concentration and a second conductivity type opposite the first conductivity type disposed in said substrate at the surface and at opposite sides of said gate electrode at respective spacings from said gate electrode; first and second regions of the second conductivity type, each of the first and second regions of the second conductivity type having a lower dopant impurity concentration than said source and drain regions, said first and second regions of the second conductivity type being respectively disposed in said substrate at the surface between said source region and said gate electrode and between said drain region and said gate electrode, contacting said source region and drain region, respectively, and spaced from each other wherein the spacing between said source region and said gate electrode is shorter than the spacing between said drain region and said gate electrode; and a first conductivity type region within said substrate having a higher dopant impurity concentration than the first dopant impurity concentration, separating said source region and said first region of the second conductivity type from a region of said substrate having the first dopant impurity concentration.
Claim 2
Dependent Claim 245 words
A metal oxide semiconductor field effect transistor comprising: a first conductivity type semiconductor substrate having a surface and a first dopant impurity concentration; an insulating film disposed on the surface of said substrate; a gate electrode disposed on said insulating film at a region of said first conductivity type semiconductor substrate; source and drain regions having a second dopant impurity concentration and a second conductivity type opposite the first conductivity type disposed in said substrate at the surface and at opposite sides of said gate electrode at respective spacings from said gate electrode; first and second regions of the second conductivity type, each of the first and second regions of the second conductivity type having a lower dopant impurity concentration than said source and drain regions, said first and second regions of the second conductivity type being respectively disposed in said substrate at the surface between said source region and said gate electrode and between said drain region and said gate electrode, contacting said source region and drain region, respectively, and spaced from each other wherein the spacing between said source region and said gate electrode is shorter than the spacing between said drain region and said gate electrode; and a first conductivity type region within said substrate having a higher dopant impurity concentration than the first dopant impurity concentration, separating said source region and said first region of the second conductivity type from a region of said substrate having the first dopant impurity concentration.
Claim 3
Dependent Claim 24 words
The metal oxide semiconductor field effect transistor of claim 1 comprising side wall insulating films at opposite sides and contacting of said gate electrode.
Claim 4
Dependent Claim 77 words
The metal oxide semiconductor field effect transistor of claim 1 wherein said first region of the second conductivity type extends from said source region to a position opposite said gate electrode and said second region of the second conductivity type extends from said drain region to a position opposite said gate electrode, said first region of the second conductivity type extending along a shorter distance at the surface than said second region of the second conductivity type.
Claim 5
Dependent Claim 35 words
The metal oxide semiconductor field effect transistor of claim 1 wherein said first conductivity type region within said substrate extends to a position within said substrate at the surface opposite part of said gate electrode.

References Cited (Backward Citations)

JPS58194367A Cited
EP0402296A1 Cited
EP0514060A2 Cited
US5304827A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-09-18 1999-03-20 1999-09-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-09-18 2003-03-20 2003-09-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-09-18 2007-03-20 2007-09-19 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag