Semiconductor device provided with isolation region

Claim 2

A semiconductor device provided with an isolation region between circuit elements, comprising: a substrate having an insulation film on a surface thereof; a monocrystalline semiconductor layer disposed on said substrate with said insulation film interposed therebetween, said monocrystalline semiconductor layer being partitioned into a plurality of islands for circuit element formation by trenches extending to said insulation film from a surface of said monocrystalline semiconductor layer, and said trenches being provided around said islands for circuit element formation, respectively; insulation layers each for burying a corresponding trench therein; a region, for capacitive coupling prevention, formed of a monocrystalline semiconductor substance which forms said monocrystalline semiconductor layer, said region for capacitive coupling prevention being disposed between said plurality of islands for circuit element formation and independent from said plurality of islands for circuit element formation by said trenches; and means for applying a constant electric potential to said region for capacitive coupling prevention.

Claim 3

A semiconductor device according to claim 1, wherein each of said insulation layers is composed of an oxide film and polycrystalline silicon filled in the interior of said oxide film.

Claim 4

A semiconductor device provided with an isolation region between circuit elements, comprising: a substrate having an insulation film on a surface thereof; a monocrystalline semiconductor layer disposed on said substrate with said insulation film interposed therebetween, said monocrystalline semiconductor layer being divided into a plurality of islands for circuit element formation by trenches each extending to said insulation film from a surface of said monocrystalline semiconductor layer, and each of said trenches being provided around each of said plurality of islands for circuit element formation; insulation layers burying said trenches, respectively; a region, for capacitive coupling prevention, formed of a one conductivity type monocrystalline semiconductor substance which forms said monocrystalline semiconductor layer, said region for capacitive coupling prevention being disposed between said plurality of islands for circuit element formation and independent from said plurality of islands for circuit element formation by said trenches; means for applying a constant electric potential to said region for capacitive coupling prevention; and a semiconductor layer of said one conductivity type formed at a lower surface of said monocrystalline semiconductor layer constructing said region for capacitive coupling prevention and having a concentration higher than said monocrystalline semiconductor layer forming said region for capacitive coupling prevention.

Claim 5

A semiconductor device provided with an isolation region between circuit elements, comprising: a substrate having an insulation film on a surface thereof; a monocrystalline semiconductor layer disposed on said substrate with said insulation film interposed therebetween, said monocrystalline semiconductor layer being divided into a plurality of islands for circuit element formation by trenches each extending to said insulation film from a surface of said monocrystalline semiconductor layer, and each of said trenches being provided around each of said plurality of islands for circuit element formation; insulation layers burying said trenches, respectively; a region, for capacitive coupling prevention, formed of a one conductivity type monocrystalline semiconductor substance which forms said monocrystalline semiconductor layer, said region for capacitive coupling prevention being disposed between said plurality of islands for circuit element formation and independent from said plurality of islands for circuit element formation by said trenches; means for applying a constant electric potential to said region for capacitive coupling prevention; and a semiconductor layer of said one conductivity type formed at a lower surface of said monocrystalline semiconductor layer constructing said region for capacitive coupling prevention and having a concentration higher than said monocrystalline semiconductor layer forming said region for capacitive coupling prevention.

Claim 6

A semiconductor device as claimed in claim 3, wherein at least one of said islands for circuit element formation has and N + emitter region, a P + (base region), an N - collector region, and a P + diffusion region for extracting excessive carriers formed in said N - collector region.

Claim 7

A semiconductor device as claimed in claim 4, wherein an oxide film is formed on a surface of said monocrystalline semiconductor layer forming said one of said islands for circuit element formation, and a plate electrode is disposed on said oxide film between said P + diffusion base region for extracting excessive carriers.

Claim 8

A semiconductor device as claimed in claim 5, wherein a contact region of one conductivity type with high concentration is formed at a surface of said region for capacitive coupling preventing, and said contact region and said plate electrode are electrically connected, and electric potential of said region for capacitive coupling prevention being maintained in a high level.

Claim 9

A semiconductor device according to claim 3, wherein each of said insulation layers is composed of an oxide film and polycrystalline silicon filled in the interior of said oxide film.

Claim 10

A semiconductor device comprising: an insulation film; a monocrystalline semiconductor substrate provided on said insulation film; said monocrystalline semiconductor substrate having at least two of first island regions for circuit element formation and a second island region disposed between said first island regions and surrounding each of said first island regions with trenches disposed therebetween, said trenches surrounding said first island regions, respectively; insulation layers filled in said respective trenches to surround said first island regions for circuit element formation, respectively; an applying means for applying a constant electric potential to said second island a region, whereby said second island region functions as a region for capacitive coupling prevention formed of monocrystalline semiconductor material; and a high impurity concentration region entirely formed in said second island region.

Claim 11

A semiconductor device comprising: an insulation film; a monocrystalline semiconductor substrate provided on said insulation film; said monocrystalline semiconductor substrate having at least two of first island regions for circuit element formation and a second island region disposed between said first island regions and surrounding each of said first island regions with trenches disposed therebetween, said trenches surrounding said first island regions, respectively; insulation layers filled in said respective trenches to surround said first island regions for circuit element formation, respectively; an applying means for applying a constant electric potential to said second island a region, whereby said second island region functions as a region for capacitive coupling prevention formed of monocrystalline semiconductor material; and a high impurity concentration region entirely formed in said second island region.

Claim 12

A semiconductor device as claimed in claim 8, wherein at least one of said first island regions has an N + emitter region, a P + base region and an N - collector region, a P + diffusion region for extracting excessive carriers being formed in said N - collector region.

Claim 13

A semiconductor device as claimed in claim 9, further comprising an oxide film formed on a surface of said semiconductor substrate forming said one of said first island regions, and a plate electrode provided on said oxide film between said P + base region and said P + diffusion region for extracting excessive carriers.

Claim 14

A semiconductor device as claimed in claim 10, further comprising a contact region of one conductivity type with high concentration formed at a surface of said second island region, and wherein said contact region and said plate electrode are electrically connected and an electric potential of said second island region is maintained in a high level.

Claim 15

A semiconductor device as claimed in claim 8, wherein said second island region has a carrier concentration distribution equal to carrier concentration distribution in said first island region.

Claim 16

A semiconductor device as claimed in claim 12, wherein said high impurity concentration region entirely formed in said second island region is located at a bottom side of said monocrystalline semiconductor substrate of said second island region and said first island region has a high impurity concentration region located at a bottom side thereof, whereby both said carrier concentration distribution in said second island region and said carrier concentration distribution in said first island region become higher in carrier density at said respective bottom side.

Claim 17

A semiconductor device according to claim 8, wherein each of said insulation layers is composed of an oxide film and polycrystalline silicon filled in the interior of said oxide film.

Claim 18

A semiconductor device as claimed in claim 8, wherein said high impurity concentration region entirely formed in said second island region is located at a bottom side of said monocrystalline semiconductor substrate of said second island region.

Claim 19

A semiconductor device as claimed in claim 15, wherein said first island region has a high impurity concentration region located at a bottom side thereof.

Claim 20

A semiconductor device in which plural circuit elements are formed on a silicon substrate provided on an insulation film, the semiconductor device comprising: first and second islands for circuit element formation formed of a monocrystalline material of said silicon substrate arranged on said insulation film; first and second insulation portions surrounding said first and second islands for circuit element formation, respectively; and a region for capacitive coupling prevention disposed between said first and second insulation portions and applied thereto to be maintained in a constant electric potential, said region for capacitive coupling prevention being formed of the monocrystalline material of said silicon substrate.

Claim 21

A semiconductor device in which plural circuit elements are formed on a silicon substrate provided on an insulation film, the semiconductor device comprising: first and second islands for circuit element formation formed of a monocrystalline material of said silicon substrate arranged on said insulation film; first and second insulation portions surrounding said first and second islands for circuit element formation, respectively; and a region for capacitive coupling prevention disposed between said first and second insulation portions and applied thereto to be maintained in a constant electric potential, said region for capacitive coupling prevention being formed of the monocrystalline material of said silicon substrate.

Claim 22

A semiconductor device as claimed in claim 17, wherein each of said first and second insulation portions is composed of a silicon oxide film and polycrystalline silicon filled in the interior of said silicon oxide film.