Patent US5448520A successfully refreshed from Google Patents.
US5448520A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Renesas Electronics Corp
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Filing: 1994-09-15
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Granted: 1995-09-05
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Expires: 2014-09-15
Abstract
Abstract A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed irk the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
Inventors
- 👤 Katsuhiro Shimohigashi
- 👤 Hiroo Masuda
- 👤 Kunihiko Ikuzaki
- 👤 Hiroshi Kawamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4096; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/30; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
311 words
A semiconductor memory comprising: a pair of data lines which are formed substantially in parallel to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said data lines of said pair of data lines; a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said data lines; an amplifier, coupled to said pair of data lines, adapted to amplify a potential difference between said data lines so as to provide said data lines with a high-level potential and a low-level potential, respectively, wherein said amplifier includes a pair of N-channel MOS transistors and a pair of P-channel MOS transistors, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, and wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines; and a precharging circuit adapted to set said data lines at a predetermined level when said plurality of dynamic memory cells are in a non-selected state, wherein said predetermined level is an intermediate level between said high-level potential and said low-level potential.
Claim 2
Dependent Claim
311 words
A semiconductor memory comprising: a pair of data lines which are formed substantially in parallel to each other; a plurality of word lines, each of which is arranged so as to intersect with both of said data lines of said pair of data lines; a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said data lines; an amplifier, coupled to said pair of data lines, adapted to amplify a potential difference between said data lines so as to provide said data lines with a high-level potential and a low-level potential, respectively, wherein said amplifier includes a pair of N-channel MOS transistors and a pair of P-channel MOS transistors, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, and wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines; and a precharging circuit adapted to set said data lines at a predetermined level when said plurality of dynamic memory cells are in a non-selected state, wherein said predetermined level is an intermediate level between said high-level potential and said low-level potential.
Claim 3
Dependent Claim
76 words
A semiconductor memory according to claim 1, further comprising: a first switching MOS transistor of N-channel type having a drain coupled to a source of each of said pair of N-channel MOS transistors and a source coupled to a first potential terminal; and a second switching MOS transistor of P-channel type having a drain coupled to a source of each of said pair of P-channel MOS transistors and a source coupled to a second potential terminal.
Claim 4
Dependent Claim
62 words
A semiconductor memory according to claim 2, wherein said precharging circuit includes a third switching MOS transistor having a source-drain path provided between said pair of data lines, and wherein said third switching MOS transistor is controlled so that said pair of data lines are electrically coupled to each other when said plurality of dynamic memory cells are in said non-selected state.
Claim 5
Dependent Claim
36 words
A semiconductor memory according to claim 3, wherein said first potential terminal has a potential level corresponding to said low-level potential, and wherein said second potential terminal has a potential level corresponding to said high-level potential.
Claim 6
Dependent Claim
66 words
A semiconductor memory according to claim 4, further comprising a control circuit adapted to supply control signals to a gate of said first switching MOS transistor and a gate of said second switching MOS transistor, respectively, so that operation of said pair of N-channel MOS transistors is started at a time different from the time when operation of said pair of P-channel MOS transistors is started.
Claim 7
Dependent Claim
67 words
A semiconductor memory according to claim 4, further comprising a fourth switching MOS transistor of N-channel type having a drain coupled to said source of each of said pair of N-channel MOS transistors and a source coupled to said first potential terminal, wherein said fourth switching MOS transistor is turned "on" at a time different from the time when said first switching MOS transistor is turned "on".
References Cited (Backward Citations)
US5383158A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |