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US5448114A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor flipchip packaging having a perimeter wall

Assignee: Toshiba Corp
•
Filing: 1995-02-15
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Granted: 1995-09-05
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Expires: 2015-02-15
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Abstract

Abstract A semiconductor device contains a semiconductor chip and a circuit board. The chip has a first surface at which the main region is formed. On the surface, a plurality of chip electrodes and a perimeter electrode surrounding the chip electrodes are formed. Bumps and a wall member made of solder metal are formed on the chip electrodes and frame-shaped electrode, respectively. The circuit board has a first surface facing the first surface of the chip. On the first surface of the circuit board, a plurality of board electrodes and a perimeter electrode are placed so as to correspond to the chip electrodes and the perimeter electrode. In a state where the chip and the board face each other, heat treatment is performed to connect the bumps and wall member to the board simultaneously by reflow. The wall member connects the chip to the board while surrounding the main region and the bumps continuously, to form essentially a closed space between the chip and the board.

Inventors

  • 👤 You Kondoh
  • 👤 Masayuki Saito
  • 👤 Takasi Togasaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 17:17
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W76/00; H10W76/60; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W70/67; H10W70/68; H10W70/682; H10W70/685; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/071; H10W72/072; H10W72/07221; H10W72/07231; H10W72/07236; H10W72/20; H10W72/221; H10W72/227; H10W72/251; H10W72/252; H10W72/29; H10W72/30; H10W72/331; H10W72/332; H10W72/341; H10W72/347; H10W72/348; H10W72/351; H10W72/352; H10W72/851; H10W72/853; H10W72/856; H10W72/874; H10W72/884; H10W72/90; H10W72/921; H10W72/926; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 258 words
A semiconductor device comprising: a semiconductor chip having a first surface at which a pixel area is formed; a plurality of chip electrodes formed on said first surface of said chip around said pixel area; a transparent board provided so as to face said chip, said board having a first surface which faces said first surface of said chip; a plurality of board electrodes provided on said board so as to correspond to said chip electrodes; a plurality of bumps for connecting said chip electrodes to said board electrodes on a one-to-one basis, said bumps being made of a solder metal; wiring layers formed on said first surface of said board and connected to said chip electrodes through said bumps and board electrodes; and a wall member connecting said first surface of said chip to said first surface of said board, and arranged to be surrounded by said bumps and to continuously surround said pixel area so as to form an essentially closed space between said chip and said board, said wall member being made of a material which has a coefficient of thermal expansion the same as or similar to that of said solder metal of said bumps so as to contribute to the connection between said chip and said board and undertake stress caused by a thermal effect applied to said device, and which transfers heat generated in said pixel area to said board so as to increase a temperature of said first surface of said board and prevent dew condensation thereon in said closed space.
Claim 2
Dependent Claim 258 words
A semiconductor device comprising: a semiconductor chip having a first surface at which a pixel area is formed; a plurality of chip electrodes formed on said first surface of said chip around said pixel area; a transparent board provided so as to face said chip, said board having a first surface which faces said first surface of said chip; a plurality of board electrodes provided on said board so as to correspond to said chip electrodes; a plurality of bumps for connecting said chip electrodes to said board electrodes on a one-to-one basis, said bumps being made of a solder metal; wiring layers formed on said first surface of said board and connected to said chip electrodes through said bumps and board electrodes; and a wall member connecting said first surface of said chip to said first surface of said board, and arranged to be surrounded by said bumps and to continuously surround said pixel area so as to form an essentially closed space between said chip and said board, said wall member being made of a material which has a coefficient of thermal expansion the same as or similar to that of said solder metal of said bumps so as to contribute to the connection between said chip and said board and undertake stress caused by a thermal effect applied to said device, and which transfers heat generated in said pixel area to said board so as to increase a temperature of said first surface of said board and prevent dew condensation thereon in said closed space.
Claim 3
Dependent Claim 13 words
The device according to claim 1, wherein said board is made of glass.
Claim 4
Dependent Claim 31 words
The device according to claim 1, wherein said wall member is made of a solder metal as said material and provided so as not to be in contact with said bumps.
Claim 5
Dependent Claim 25 words
The device according to claim 3, wherein said solder metal of said wall member is essentially the same as said solder metal of said bumps.
Claim 6
Dependent Claim 61 words
The device according to claim 1, further comprising a first connection layer made of a material essentially the same as that of said chip electrodes and provided between said chip and said wall member, and a second connection layer made of a material essentially the same as that of said board electrodes and provided between said board and said wall member.
Claim 7
Dependent Claim 26 words
The device according to claim 1, further comprising a resin sealing layer provided between said chip and said board so as to surround said wall member.

References Cited (Backward Citations)

US3871015A Cited
US3591839A Cited
US4604644A Cited
US4710798A Cited
US4942140A Cited
US5021888A Cited
US5071787A Cited
JPH0451057A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-09-04 1999-03-06 1999-09-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-09-04 2003-03-06 2003-09-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-09-04 2007-03-06 2007-09-05 $7700.00 Window Closed / Lapsed

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