Current-summing digital-to-analog converter with binarily weighted current sources

Claim 2

A current-summing digital-to-analog converter, comprising: a bias block that provides first and second voltage outputs; at least one bit cell for receiving a binary input signal, including: a switch to selectively connect either a first or a second summing node to a current flow path depending upon a state of the binary input signal; an output bipolar transistor and a current source, connected in series on a collector node between a supply voltage and a reference potential; a first MOS transistor connected in said current flow path, said MOS transistor having a gate connected to a junction between the current source and the bipolar transistor and a source connected to the base of the bipolar transistor; a base current compensating second MOS transistor connected between the supply voltage and a base of said output bipolar transistor, said base current compensating second MOS transistor having a gate connected to the first voltage output of said bias block; and a resistor connected between the base of said output bipolar transistor and the second voltage output of said bias block.

Claim 3

The digital-to-analog converter of claim 1 wherein said at least one bit cell comprises a plurality of bit cells connected in parallel and arranged in a bit order, and wherein said current sources of each respective bit cell are binarily weighted.

Claim 4

The digital-to-analog converter of claim 2 wherein the resistor of each of said plurality of bit cells having resistance according to a position of its associated cell in said bit order.

Claim 5

The digital-to-analog converter of claim 3 wherein the resistor of each of said plurality of bit cells having resistance as a power of 2 according to a position of its associated cell in said bit order.

Claim 6

The digital to analog converter of claim 3 wherein the resistor of each of said plurality of bit cells, except a most significant bit cell has a resistance 2 times larger than the resistor of the most significant bit cell, and further comprising a plurality of resistors each of a resistance equal to the resistor of most significant bit cell, each connected between an end of a resistor of each bit cell and an end of resistor of an adjacent bit cell as a R-2R network.

Claim 7

The digital-to-analog converter of claim 1 wherein said bipolar transistors are of substantially the same size.

Claim 8

The digital-to-analog converter of claim 1 wherein said bipolar transistor are NPN transistors, and wherein said MOS transistors are NMOS transistors.

Claim 9

The digital-to-analog converter of claim 1 wherein the bias block and the at least one bit cell form a current amplifier.

Claim 10

The digital-to-analog converter of claim 8 wherein the current amplifier is a resistor ratioed current amplifier.

Claim 11

The digital-to-analog converter of claim 1 wherein the bias block comprises a voltage to current converter.

Claim 12

The digital-to-analog converter of claim 1 wherein the bias block comprises a bandgap voltage generator.

Claim 13

The digital-to-analog converter of claim 1 wherein the switch comprises a pair of switch transistors connected respectively between the first and second summing node and the current flow path, each switch transistor having a current control element connected to receive respectively an input binary signal and a complement of the input binary signal.

Claim 14

The digital-to-analog converter of claim 12 wherein the pair of switch transistors are MOS transistors.

Claim 15

The digital-to-analog converter of claim 12 wherein the pair of switch transistors are NMOS transistors.

Claim 16

The digital-to-analog converter of claim 1 wherein the switch comprises a pair of switch transistors connected respectively between the first and second summing node and the current flow path, each switch transistor having a current control element, the control element of one switch transistor being connected to the output bipolar transistor, and the control element of another switch transistor being connected to receive respectively an input binary signal.

Claim 17

The digital-to-analog converter of claim 15 wherein the pair of switch transistors are MOS transistors.

Claim 18

The digital-to-analog converter of claim 16 wherein the pair of MOS transistors are NMOS transistors.

Claim 19

A digital-to-analog converter, comprising: a bias block, including: first and second current paths between a supply voltage and a reference potential, each having a reference current source and a bipolar transistor in series; a third current path having an MOS transistor between the supply voltage and a base of the bipolar transistor of the first current path; a fourth current path having an MOS transistor between the supply voltage and a base of the bipolar transistor of the second current path; a gate of the MOS transistors of said third and fourth current paths being connected to a node within the second current path; a fifth current path having an MOS transistor between the supply voltage and a summation node, a gate of the MOS transistor of the fifth current path being connected to a node within said first current path; a first resistor between the base of the bipolar transistor of the first current path and the summation node; and a summation current source between the summation node and a reference potential; a bit cell, including: sixth current path between the supply voltage and the reference potential having a reference current source and a bipolar transistor in series; a seventh current path having an MOS transistor between the supply voltage and a base of the bipolar transistor of the sixth current path, the MOS transistor of the seventh current path having a gate connected to a node within the second current path; a second resistor between the base of the bipolar transistor of the sixth current path and the summation node; an eighth current path having an MOS transistor between a switch node and the base of the bipolar transistor of the sixth current path, the MOS transistor of the eighth current path being connected to a node within the sixth current path; a switch connected to selectively connect the switch node to either a first or a second output summing node according to a state of a binary signal to be converted.

Claim 20

A digital-to-analog converter, comprising: a bias block, including: first and second current paths between a supply voltage and a reference potential, each having a reference current source and a bipolar transistor in series; a third current path having an MOS transistor between the supply voltage and a base of the bipolar transistor of the first current path; a fourth current path having an MOS transistor between the supply voltage and a base of the bipolar transistor of the second current path; a gate of the MOS transistors of said third and fourth current paths being connected to a node within the second current path; a fifth current path having an MOS transistor between the supply voltage and a summation node, a gate of the MOS transistor of the fifth current path being connected to a node within said first current path; a first resistor between the base of the bipolar transistor of the first current path and the summation node; and a summation current source between the summation node and a reference potential; a bit cell, including: sixth current path between the supply voltage and the reference potential having a reference current source and a bipolar transistor in series; a seventh current path having an MOS transistor between the supply voltage and a base of the bipolar transistor of the sixth current path, the MOS transistor of the seventh current path having a gate connected to a node within the second current path; a second resistor between the base of the bipolar transistor of the sixth current path and the summation node; an eighth current path having an MOS transistor between a switch node and the base of the bipolar transistor of the sixth current path, the MOS transistor of the eighth current path being connected to a node within the sixth current path; a switch connected to selectively connect the switch node to either a first or a second output summing node according to a state of a binary signal to be converted.

Claim 21

The digital-to-analog converter of claim 18 wherein said reference current sources supply substantially equal currents.

Claim 22

The digital-to-analog converter of claim 18 wherein said bipolar transistors are NPN transistors.

Claim 23

The digital-to-analog converter of claim 18 wherein said MOS transistors are NMOS transistors.

Claim 24

The digital-to-analog converter of claim 18 wherein said at least one bit cell comprises a plurality of bit cells arranged in a bit order and connected in parallel.

Claim 25

The digital-to-analog converter of claim 22 wherein the resistor of each of said plurality of bit cells has a resistance according to a position of its associated cell in said bit order.

Claim 26

The digital-to-analog converter of claim 23 wherein the resistor of each of said plurality of bit cells has a resistance as a power of 2 according to a position of its associated cell in said bit order.

Claim 27

The digital-to-analog converter of claim 23 wherein the resistor of each of said plurality of bit cells, except a most significant bit cell, has a resistance 2 times larger than the resistor of the most significant bit cell, and further comprising a plurality of resistors each of a resistance equal to the resistor of said most significant bit cell, each connected between an end of a resistor of each bit cell and an end of resistor of an adjacent bit cell as an R-2R network.

Claim 28

The digital-to-analog converter of claim 18 wherein said bipolar transistors are of substantially identical size.

Claim 29

The digital-to-analog converter of claim 18 wherein said bipolar transistors are NPN transistors, and wherein said MOS transistors are NMOS transistors.

Claim 30

The digital-to-analog converter of claim 18 wherein the switch comprises a pair of switch transistors connected respectively between the first and second output summing node and the switch node, each switch transistor having a current control element connected to receive respectively an input binary signal and a complement of the input binary signal.

Claim 31

The digital-to-analog converter of claim 28 wherein the pair of switch transistors are MOS transistors.

Claim 32

The digital-to-analog converter of claim 28 wherein the pair of switch transistors are NMOS transistors.

Claim 33

The digital-to-analog converter of claim 18 wherein the switch comprises a pair of switch transistors connected respectively between the first and second output summing node and the switch node, each switch transistor having a current control element, the control element of one switch transistor being connected to the output bipolar transistor, and the control element of another switch transistor being connected to receive respectively an input binary signal.

Claim 34

The digital-to-analog converter of claim 31 wherein the pair of switch transistors are MOS transistors.

Claim 35

The digital-to-analog converter of claim 32 wherein the pair of MOS transistors are NMOS transistors.