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US5445991A
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Method for fabricating a semiconductor device using a porous silicon region
Assignee: KYUNG POOK NATIONAL UNIVERSITY SENSOR TECHNOLOGY RESEARCH CENTER
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Filing: 1994-12-23
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Granted: 1995-08-29
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Expires: 2014-12-23
Abstract
Abstract A method for fabricating a silicon diaphragm comprises the steps of preparing an n-type silicon substrate; diffusing n + impurities in the silicon substrate to form an n + diffusion region in a part of the upper wall thereof; growing an n-type silicon epitaxial layer thereon; forming a through-hole in the n-type silicon epitaxial layer to expose a part of the n + diffusion region; performing an anodic reaction in an HF solution to make the n + diffusion region a porous silicon layer; etching the porous silicon layer to form an air-gap;and, sealing the through-hole.
Inventors
- 👤 Jong H. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:26
CPC Classifications
G; G01; G01L; G01L9/00; G01L9/0041; G01L9/0042; H; H10; H10D; H10D48/00; H10D48/50; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6349; H10P14/65; H10P14/6502; H10P14/6508; H10P30/00; H10P30/20; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/072
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
103 words
A method for manufacturing a silicon diaphragm using a porous silicon, the method comprising the steps of: preparing an n-type silicon substrate; diffusing n + impurities in the silicon substrate to form an n + diffusion region in a part of the upper wall thereof; growing an n-type silicon epitaxial layer thereon; forming a through-hole in the n-type silicon epitaxial layer to expose a part of the n + diffusion region; performing an anodic reaction in an HF solution to make the n + diffusion region a porous silicon layer; etching the porous silicon layer to form an air-gap; and, sealing the through-hole.
Claim 2
Independent Claim
103 words
A method for manufacturing a silicon diaphragm using a porous silicon, the method comprising the steps of: preparing an n-type silicon substrate; diffusing n + impurities in the silicon substrate to form an n + diffusion region in a part of the upper wall thereof; growing an n-type silicon epitaxial layer thereon; forming a through-hole in the n-type silicon epitaxial layer to expose a part of the n + diffusion region; performing an anodic reaction in an HF solution to make the n + diffusion region a porous silicon layer; etching the porous silicon layer to form an air-gap; and, sealing the through-hole.
Claim 3
Independent Claim
136 words
A method for manufacturing a silicon pressure sensor using a porous silicon, the method comprising the steps of: preparing an n-type silicon substrate; diffusing n + impurities in the silicon substrate to form an n + diffusion region in a part of the upper wall thereof; growing an n-type silicon epitaxial layer thereon; forming a piezo-resistor in the n-type silicon epitaxial layer; forming a Ni/Cr/Au metallic layer on the n-type silicon epitaxial layer using an evaporating process; forming a through-hole in the Ni/Cr/Au metallic and n-type silicon epitaxial layer to expose a part of the n + diffusion region; performing an anodic reaction in an HF solution to make the n + diffusion region a porous silicon layer; patterning the Ni/Cr/Au metallic layer; etching the porous silicon layer to form an air-gap; and, sealing the through-hole.
Claim 4
Independent Claim
136 words
A method for manufacturing a silicon pressure sensor using a porous silicon, the method comprising the steps of: preparing an n-type silicon substrate; diffusing n + impurities in the silicon substrate to form an n + diffusion region in a part of the upper wall thereof; growing an n-type silicon epitaxial layer thereon; forming a piezo-resistor in the n-type silicon epitaxial layer; forming a Ni/Cr/Au metallic layer on the n-type silicon epitaxial layer using an evaporating process; forming a through-hole in the Ni/Cr/Au metallic and n-type silicon epitaxial layer to expose a part of the n + diffusion region; performing an anodic reaction in an HF solution to make the n + diffusion region a porous silicon layer; patterning the Ni/Cr/Au metallic layer; etching the porous silicon layer to form an air-gap; and, sealing the through-hole.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |