Patent US5445976A successfully refreshed from Google Patents.
US5445976A
Expired / Lapsed
US
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Method for producing bipolar transistor having reduced base-collector capacitance
Assignee: Texas Instruments Inc
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Filing: 1994-08-09
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Granted: 1995-08-29
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Expires: 2014-08-09
Abstract
Abstract The invention described herein includes, in one of its forms, a method for fabricating a bipolar transistor having a reduced base-collector capacitance. A specific embodiment includes forming a selectively etchable material 44 over a highly doped subcollector layer 42, removing portions of the selectively etchable material 44 and then growing collector 46, base 48, and emitter 50 layers over the structure. The selectively etchable material 44 may then be removed to form an undercut region between the highly doped subcollector layer 42 and the highly doped base 48. The structure provides the advantage of improved high-frequency and high-power operation.
Inventors
- 👤 Timothy S. Henderson
- 👤 Darrell G. Hill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:33
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/13; H10D62/137; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/072
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
114 words
A method of fabricating an electronic device comprising the steps of: a. providing a material structure comprising: a first layer; and a second layer adjacent to said first layer; b. removing portions of said second layer to expose said first layer and to form an opening in said second layer; c. forming a third layer which fills said opening; d. forming a fourth layer over said third layer; e. removing portions of said second, third, and fourth layers to expose an edge of said second layer; f. removing remaining portions of said second layer, whereby a capacitance between said fourth layer and said first layer is reduced by the removal of said second layer.
Claim 2
Independent Claim
114 words
A method of fabricating an electronic device comprising the steps of: a. providing a material structure comprising: a first layer; and a second layer adjacent to said first layer; b. removing portions of said second layer to expose said first layer and to form an opening in said second layer; c. forming a third layer which fills said opening; d. forming a fourth layer over said third layer; e. removing portions of said second, third, and fourth layers to expose an edge of said second layer; f. removing remaining portions of said second layer, whereby a capacitance between said fourth layer and said first layer is reduced by the removal of said second layer.
Claim 3
Dependent Claim
42 words
The method of claim 1 wherein said electronic device is a bipolar transistor and said first layer is a subcollector layer, said second layer is an etch layer, said third layer is a collector layer, said fourth layer is a base layer.
Claim 4
Dependent Claim
35 words
The method of claim 2 wherein said etch layer is chosen from the group of compound semiconductors consisting of aluminum arsenide, aluminum gallium arsenide wherein said aluminum content is greater than approximately 40%, and GaInP.
Claim 5
Dependent Claim
30 words
The method of claim 2 wherein said step of growing said third layer comprises growing said third layer in said space and over a top surface of said etch layer.
Claim 6
Dependent Claim
22 words
The method of claim 2 wherein said step of growing said third layer comprises growing said third layer only in said space.
Claim 7
Dependent Claim
26 words
The method claim 1 further comprising the step of forming a layer of material over said fourth layer, said layer of material being in tensile stress.
Claim 8
Dependent Claim
13 words
The method of claim 6 wherein said layer of material is a dielectric.
Claim 9
Dependent Claim
11 words
The method of claim 7 wherein said dielectric is silicon nitride.
Claim 10
Independent Claim
115 words
A method for fabricating a bipolar transistor comprising the steps of: a. providing a material structure comprising a first layer; b. removing portions of said first layer to form a mesa; c. forming a second layer to replace said portions of said first layer removed in step (b); d. forming a third layer over said mesa and said second layer; e. forming a fourth layer over said third layer; f. removing portions of said second, third, and fourth layers to expose an edge of said second layer; g. removing remaining portions of said second layer, whereby a capacitance between said fourth layer and said first layer is reduced by the removal of said second layer.
Claim 11
Independent Claim
115 words
A method for fabricating a bipolar transistor comprising the steps of: a. providing a material structure comprising a first layer; b. removing portions of said first layer to form a mesa; c. forming a second layer to replace said portions of said first layer removed in step (b); d. forming a third layer over said mesa and said second layer; e. forming a fourth layer over said third layer; f. removing portions of said second, third, and fourth layers to expose an edge of said second layer; g. removing remaining portions of said second layer, whereby a capacitance between said fourth layer and said first layer is reduced by the removal of said second layer.
Claim 12
Dependent Claim
42 words
The method of claim 9 wherein said electronic device is a bipolar transistor and said first layer is a subcollector layer, said second layer is an etch layer, said third layer is a collector layer, said fourth layer is a base layer.
Claim 13
Dependent Claim
35 words
The method of claim 10 wherein said etch layer is chosen from the group of compound semiconductor consisting of aluminum arsenide, aluminum gallium arsenide wherein said aluminum content is greater than approximately 40%, and GaInP.
Claim 14
Dependent Claim
26 words
The method claim 9 further comprising the step of forming a layer of material over said fourth layer, said layer of material being in tensile stress.
Claim 15
Dependent Claim
13 words
The method of claim 12 wherein said layer of material is a dielectric.
Claim 16
Dependent Claim
11 words
The method of claim 13 wherein said dielectric is silicon nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |