CMOS input stage

Claim 2

A CMOS input stage for operation with a supply voltage selectively having a first value or a second higher value, comprising: a supply voltage terminal selectively receiving a first value or a second value of a supply voltage during operation, a reference potential terminal, and an input terminal; a first field effect transistor of a first conduction type having a load path and a gate terminal, and a second field effect transistor of a second conduction type having a load path and a gate terminal; the load paths of said field effect transistors being connected in series between said supply voltage terminal and said reference potential terminal; an output terminal of the CMOS input stage formed between said first and second field effect transistors; the gate terminals of said field effect transistors being connected to said input terminal; control means for adjusting a resistance of the load path of at least one of said field effect transistors as a function of a particular value selected for the supply voltage; a connection terminal for a threshold reversal signal; said control means having two further field effect transistors of the second conduction type with load paths and gate terminals; the load paths of said further field effect transistors being connected in a series circuit, said series circuit being parallel to the load path of said second field effect transistor; and the gate terminal of one of said further field effect transistors being connected to said input terminal, and the gate terminal of the other of said further field effect transistors being connected to said connection terminal for the threshold reversal signal.

Claim 3

A CMOS input stage for operation with a supply voltage selectively having a first value or a second higher value, comprising: a supply voltage terminal selectively receiving a first value or a second value of a supply voltage during operation, a reference potential terminal, and an input terminal; a first field effect transistor of a first conduction type having a load path and a gate terminal, and a second field effect transistor of a second conduction type having a load path and a gate terminal; the load paths of said field effect transistors being connected in series between said supply voltage terminal and said reference potential terminal; an output terminal of the CMOS input stage formed between said first and second field effect transistors; the gate terminals of said field effect transistors being connected to said input terminal; control means for adjusting a resistance of the load path of at least one of said field effect transistors as a function of a particular value selected for the supply voltage; a connection terminal for a threshold reversal signal; said control means having two further field effect transistors of the first conduction type with load paths and gate terminals; the load paths of said further field effect transistors being connected in parallel and being connected between said supply voltage terminal and the series connection of the load paths of said first and second field effect transistors; the gate terminal of one of said further field effect transistors being connected to the input terminal, and the gate terminal of the other of said further field effect transistors being connected to said connection terminal for the threshold reversal signal.

Claim 4

A CMOS input stage for operation with a supply voltage selectively having a first value or a second higher value, comprising: a supply voltage terminal selectively receiving a first value or a second value of a supply voltage during operation, a reference potential terminal, and an input terminal; a first field effect transistor of a first conduction type having a load path and a gate terminal, and a second field effect transistor of a second conduction type having a load path and a gate terminal; the load paths of said field effect transistors being connected in series between said supply voltage terminal and said reference potential terminal; an output terminal of the CMOS input stage formed between said first and second field effect transistors; the gate terminals of said field effect transistors being connected to said input terminal; control means for adjusting a resistance of the load path of at least one of said field effect transistors as a function of a particular value selected for the supply voltage; a connection terminal for a threshold reversal signal; said control means having two further field effect transistors of the first conduction type with load paths and gate terminals; the load paths of said further field effect transistors being connected in parallel and being connected between said supply voltage terminal and the series connection of the load paths of said first and second field effect transistors; the gate terminal of one of said further field effect transistors being connected to the input terminal, and the gate terminal of the other of said further field effect transistors being connected to said connection terminal for the threshold reversal signal.

Claim 5

A CMOS buffer stage, comprising: a CMOS input stage for operation with a supply voltage selectively having a first value or a second higher value, including: a supply voltage terminal selectively receiving a first value or a second value of a supply voltage during operation, a reference potential terminal, and an input terminal; a first field effect transistor of a first conduction type having a load path and a gate terminal, and a second field effect transistor of a second conduction type having a load path and a gate terminal; the load paths of said field effect transistors being connected in series between said supply voltage terminal and said reference potential terminal; an output terminal of the CMOS input stage formed between said first and second field effect transistors; the gate terminals of said field effect transistors being connected to said input terminal; and control means for adjusting a resistance of the load path of at least one of said field effect transistors as a function of a particular value selected for the supply voltage; an inverter having an input connected downstream of an output voltage side of said CMOS input stage and having an output; and a holding field effect transistor having a load path connected parallel to the load path of said first field effect transistor and having a gate terminal being connected to the output of said inverter.

Claim 6

A CMOS buffer stage, comprising: a CMOS input stage for operation with a supply voltage selectively having a first value or a second higher value, including: a supply voltage terminal selectively receiving a first value or a second value of a supply voltage during operation, a reference potential terminal, and an input terminal; a first field effect transistor of a first conduction type having a load path and a gate terminal, and a second field effect transistor of a second conduction type having a load path and a gate terminal; the load paths of said field effect transistors being connected in series between said supply voltage terminal and said reference potential terminal; an output terminal of the CMOS input stage formed between said first and second field effect transistors; the gate terminals of said field effect transistors being connected to said input terminal; and control means for adjusting a resistance of the load path of at least one of said field effect transistors as a function of a particular value selected for the supply voltage; an inverter having an input connected downstream of an output voltage side of said CMOS input stage and having an output; and a holding field effect transistor having a load path connected parallel to the load path of said first field effect transistor and having a gate terminal being connected to the output of said inverter.

Claim 7

The CMOS buffer stage according to claim 3, wherein said CMOS input stage includes: a connection terminal for a threshold reversal signal; said control means having two further field effect transistors of the second conduction type with load paths and gate terminals; the load paths of said further field effect transistors being connected in a series circuit, said series circuit being parallel to the load path of said second field effect transistor; the gate terminal of one of said further field effect transistors being connected to said input terminal, and the gate terminal of the other of said further field effect transistors being connected to said connection terminal for the threshold reversal signal.

Claim 8

The CMOS buffer stage according to claim 3, wherein said CMOS input stage includes: a connection terminal for a threshold reversal signal; said control means having two further field effect transistors of the first conduction type with load paths and gate terminals; the load paths of said further field effect transistors being connected in parallel and being connected between said supply voltage terminal and the series connection of the load paths of said first and second field effect transistors; the gate terminal of one of said further field effect transistors being connected to the input terminal, and the gate terminal of the other of said further field effect transistors being connected to said connection terminal for the threshold reversal signal.