Dual back-bias voltage generating circuit with switched outputs

Claim 2

A back-bias voltage generating circuit of a semiconductor device for applying a back-bias voltage to a back-bias terminal and for lowering the voltage of the back-bias terminal, comprising: a driving signal generating circuit receiving oscillating signals from an oscillator, the driving signal generating circuit generating first and second input driving signals of alternating low and high levels; a first pumping circuit coupled to receive the first input driving signal and having a first pumping capacitor, the first pumping circuit charging a first electrode of the first pumping capacitor, wherein a second electrode of the first pumping capacitor is charged to a voltage lower than the voltage of the back-bias terminal; a second pumping circuit coupled to receive the second input driving signal and having a second pumping capacitor, the second pumping circuit charging a first electrode of the second pumping capacitor, wherein a second electrode of the second pumping capacitor is charged to a voltage lower than the voltage of the back-bias terminal; a first switching circuit coupled to the second pumping circuit and responsive to a signal received from the second pumping circuit of a voltage level higher than the voltage of the back-bias terminal, wherein the second electrode of the first pumping capacitor is coupled by the first switching circuit to the back-bias terminal during the time when the voltage on the second electrode of the first pumping capacitor is lower than the voltage of the back-bias terminal; and a second switching circuit coupled to the first pumping circuit and responsive to a signal received from the first pumping circuit of a voltage level higher than the voltage of the back-bias terminal, wherein the second electrode of the second pumping capacitor is coupled by the second switching circuit to the back-bias terminal during the time when the voltage on the second electrode of the second pumping capacitor is lower than the voltage of the back-bias terminal.

Claim 3

The back-bias voltage generating circuit as claimed in claim 1, wherein: the driving signal generating circuit comprises first and second NOR gates, the output of the first NOR gate being coupled to a first input terminal of the second NOR gate and the output of the second NOR gate being coupled to a first input terminal of the first NOR gate, a second input terminal of the first NOR gate being coupled to receive an oscillating signal from the oscillator, a second input terminal of the second NOR gate being coupled to receive the output of an inverter, wherein the input of the inverter is coupled to receive the oscillating signal from the oscillator, wherein the outputs of the first and second NOR gates generate first and second input driving signals that are substantially non-overlapping alternating signals.

Claim 4

The back-bias voltage generating circuit as claimed in claim 1, wherein: the first pumping circuit comprises a first NMOS transistor operative to ground the second electrode of the first pumping capacitor when the first electrode of the first pumping capacitor is being charged; the second pumping circuit comprises a second NMOS transistor operative to ground the second electrode of the second pumping capacitor when the first electrode of the second pumping capacitor is being charged; the first switching circuit comprises a third NMOS transistor having a gate coupled to the second NMOS transistor of the second pumping circuit; the second switching circuit comprises a fourth NMOS transistor having a gate coupled to the first NMOS transistor of the first pumping circuit; wherein the third and fourth NMOS transistors are operative to couple and decouple the second electrodes of the first and second pumping capacitors, respectively, to the back-bias terminal in a manner such that the voltage applied to the gates of the third and fourth NMOS transistors, respectively, is less than the voltage of the back-bias terminal during the time when the third and fourth transistors, respectively, are being turned off, wherein reversing current flow from the back-bias terminal to the second electrodes of the first and second pumping capacitors is prevented during turn off of the third and fourth NMOS transistors, respectively, and wherein the third and fourth NMOS transistors are operated in a high conductance state during the time when the second electrodes of the first and second pumping capacitors, respectively, are coupled to the back-bias terminal.

Claim 5

A voltage generating circuit for applying a voltage to a terminal, comprising: oscillator means for generating alternating first and second oscillating signals of alternating high and low voltage levels: a first pumping capacitor circuit coupled to receive first oscillating signal and including a first pumping capacitor having first and second electrodes, the first electrode of the first pumping capacitor being coupled to receive input signals derived from the first oscillating signal; a second pumping capacitor circuit coupled to receive the second oscillating signal and including a second pumping capacitor having first and second electrodes, the first electrode of the second pumping capacitor being coupled to receive input signals derived from the second oscillating signal; first switch means coupled to the first pumping capacitor and the second pumping circuit for selectively coupling and decoupling the second electrode of the first pumping capacitor to the terminal, the first switch means being operative in response to signals derived from the second oscillating signal; and second switch means coupled to the second pumping capacitor and the first pumping circuit for selectively coupling and decoupling the second electrode of the second pumping capacitor to the terminal, the second switch means being operative in response to signals derived from the first oscillating signal.

Claim 6

A voltage generating circuit for applying a voltage to a terminal, comprising: oscillator means for generating alternating first and second oscillating signals of alternating high and low voltage levels: a first pumping capacitor circuit coupled to receive first oscillating signal and including a first pumping capacitor having first and second electrodes, the first electrode of the first pumping capacitor being coupled to receive input signals derived from the first oscillating signal; a second pumping capacitor circuit coupled to receive the second oscillating signal and including a second pumping capacitor having first and second electrodes, the first electrode of the second pumping capacitor being coupled to receive input signals derived from the second oscillating signal; first switch means coupled to the first pumping capacitor and the second pumping circuit for selectively coupling and decoupling the second electrode of the first pumping capacitor to the terminal, the first switch means being operative in response to signals derived from the second oscillating signal; and second switch means coupled to the second pumping capacitor and the first pumping circuit for selectively coupling and decoupling the second electrode of the second pumping capacitor to the terminal, the second switch means being operative in response to signals derived from the first oscillating signal.

Claim 7

The circuit as claimed in claim 4, wherein the first and second oscillating signals are substantially non-overlapping.

Claim 8

The circuit as claimed in claim 4, wherein the terminal has a back-bias voltage, wherein the first and second switch means couple the second electrodes of the first and second pumping capacitors to the terminal, respectively, in response to a high voltage level signal, and wherein the first and second switch means decouple the second electrodes of the first and second pumping capacitors to the terminal, respectively, in response to a signal having a voltage level lower than the back-bias voltage.

Claim 9

The circuit as claimed in claim 4, wherein the terminal has a back-bias voltage, wherein the first switch means comprises a first NMOS transistor and the second switch means comprises a second NMOS transistor, the first and second NMOS transistors each having a gate to which is applied a signal for selectively coupling and decoupling the second electrode of the first and second pumping capacitors, respectively, to the terminal, wherein the first and second NMOS transistors couple the second electrodes of the first and second pumping capacitors to the terminal, respectively, in response to a high voltage level signal applied to the gates thereof, and wherein the first and second NMOS transistor decouple the second electrodes of the first and second pumping capacitors from the terminal, respectively, in response to a voltage level lower than the back-bias voltage.

Claim 10

A back-bias voltage generating circuit of a semiconductor device for applying a back-bias voltage to a back-bias terminal, comprising: a driving signal generating circuit receiving oscillating signals from an oscillator, the driving signal generating circuit generating first and second input driving signals of alternating low and high levels; a first pumping circuit coupled to receive the first input driving signal and having a first pumping capacitor, the first pumping circuit Charging a first electrode of the first pumping capacitor, wherein a second electrode of the first pumping capacitor is charged to a voltage lower than the voltage of the back-bias terminal, the first pumping circuit also generating a second switch means control signal; a second pumping circuit coupled to receive the second input driving signal and having a second pumping capacitor, the second pumping circuit charging a first electrode of the second pumping capacitor, wherein a second electrode of the second pumping capacitor is charged to a voltage lower than the voltage of the back-bias terminal, the second pumping circuit also generating a first switch means control signal; a first switching means responsive to the first switch means control signal generated by the second pumping circuit for coupling the second electrode of the first pumping capacitor to the back-bias terminal during a time when the voltage on the second electrode of the first pumping capacitor is lower than the voltage of the back-bias terminal and for decoupling the second electrode of the first pumping capacitor from the back-bias terminal; and a second switching means responsive to the second switch means control signal generated by the first pumping circuit for coupling the second electrode of the second pumping capacitor to the back-bias terminal during a time when the voltage on the second electrode of the second pumping capacitor is lower than the voltage of the back-bias terminal and for decoupling the second electrode of the second pumping capacitor from the back-bias terminal.

Claim 11

A back-bias voltage generating circuit of a semiconductor device for applying a back-bias voltage to a back-bias terminal, comprising: a driving signal generating circuit receiving oscillating signals from an oscillator, the driving signal generating circuit generating first and second input driving signals of alternating low and high levels; a first pumping circuit coupled to receive the first input driving signal and having a first pumping capacitor, the first pumping circuit Charging a first electrode of the first pumping capacitor, wherein a second electrode of the first pumping capacitor is charged to a voltage lower than the voltage of the back-bias terminal, the first pumping circuit also generating a second switch means control signal; a second pumping circuit coupled to receive the second input driving signal and having a second pumping capacitor, the second pumping circuit charging a first electrode of the second pumping capacitor, wherein a second electrode of the second pumping capacitor is charged to a voltage lower than the voltage of the back-bias terminal, the second pumping circuit also generating a first switch means control signal; a first switching means responsive to the first switch means control signal generated by the second pumping circuit for coupling the second electrode of the first pumping capacitor to the back-bias terminal during a time when the voltage on the second electrode of the first pumping capacitor is lower than the voltage of the back-bias terminal and for decoupling the second electrode of the first pumping capacitor from the back-bias terminal; and a second switching means responsive to the second switch means control signal generated by the first pumping circuit for coupling the second electrode of the second pumping capacitor to the back-bias terminal during a time when the voltage on the second electrode of the second pumping capacitor is lower than the voltage of the back-bias terminal and for decoupling the second electrode of the second pumping capacitor from the back-bias terminal.

Claim 12

The circuit as claimed in claim 8, wherein the first switching means comprises a first NMOS transistor and the second switching means comprises a second NMOS transistor, wherein the first pumping circuit comprises first PMOS transistor and third and fourth NMOS transistors connected in series between first and second power terminals, the source of the first PMOS transistor coupled to the first power terminal, and the drains of the first PMOS transistor and the third NMOS transistor coupled together and coupled to the gates of the second and fourth NMOS transistors, the source of the third NMOS transistor coupled to the drain of the fourth NMOS transistor and to the second electrode of the first pumping capacitor, the source of the fourth NMOS transistor coupled to the second power terminal.

Claim 13

The circuit as claimed in claim 9, wherein the second pumping circuit comprises second PMOS transistor and firth and sixth NMOS transistors connected in series between the first and second power terminals, the source of the second PMOS transistor coupled to the first power terminal, and the drains of the second PMOS transistor and the firth NMOS transistor coupled together and coupled to the gates of the first and sixth NMOS transistors, the source of the fifth NMOS transistor coupled to the drain of the sixth NMOS transistor and to the second electrode of the second pumping capacitor, the source of the sixth NMOS transistor coupled to the second power terminal.

Claim 14

The circuit as claimed in claim 10, further comprising first inverter means for inverting the first input driving signal, and second inverter means for inverting the second input driving signal, wherein the first input driving signal is applied to the gates of the first PMOS transistor and the third NMOS transistor and the inverted first input driving signal is applied to the first electrode of the first pumping capacitor, and wherein the second input driving signal is applied to the gates of the second PMOS transistor and the fifth NMOS transistor and the inverted second input driving signal is applied to the first electrode of the second pumping capacitor.

Claim 15

The circuit as claimed in claim 11, wherein the first and second input driving signals are substantially non-overlapping.

Claim 16

The circuit as claimed in claim 9, wherein the first and second input driving signals are substantially non-overlapping.

Claim 17

The circuit as claimed in claim 10, wherein the first and second input driving signals are substantially non-overlapping.

Claim 18

The circuit as claimed in claim 8, wherein the first and second input driving signals are substantially non-overlapping.