Linear dual switch module

Claim 2

A semiconductor switching device module of reduced inductance comprising: a housing having a baseplate and defining a chamber; a low electrical resistance plate-like first terminal member having opposed major faces, a substantially linear edge, and a first impedance; a low electrical resistance plate-like second terminal member having opposed major faces, a substantially linear edge and an impedance that is substantially similar to the impedance of said first terminal member; said first and second plate-like terminal members being closely spaced in substantial overlap, and said substantially linear edges being closely spaced and generally parallel; at least one insulated gate semiconductor switching device disposed in said chamber in close proximity to both of said substantially linear edges of said first and second plate-like terminal members: means for interconnecting said substantially linear edge of said first plate-like terminal member to an input of said semiconductor switching device, whereby input current to said semiconductor switching device can pass through said first plate-like terminal member at a first inductance; and means for interconnecting said substantially linear edge of said second plate-like terminal member to an output of said semiconductor switching device, whereby output current from said semiconductor switching device can pass through said second plate-like terminal member at a magnitude substantially equal to that of said input current and at an inductance generally similar to said first inductance; effective to form a first switch in which respective current flow inductance in said plate-like terminal members substantially negate one another.

Claim 3

The module of claim 1 wherein the plate-like terminal members are spaced by a substantially continuous dielectric layer.

Claim 4

The module of claim 2 wherein the dielectric layer is a molded plastic plate-like element having conformations on its opposite faces for respective alignment with the first and second plate-like terminal members.

Claim 5

The module of claim 2 wherein the dielectric layer is plastic and the plastic is molded between and in adhesion with facing surfaces of the first and second plate-like terminal members, effective to form a molded subassembly.

Claim 6

The module of claim 1 that further includes: a low electrical resistance plate-like third terminal member having opposed major faces, a substantially linear edge, and a first impedance; a low electrical resistance plate-like fourth terminal member having opposed major faces, a substantially linear edge and an impedance that is substantially similar to the impedance of said third terminal member; said third and fourth plate-like terminal members being closely spaced in substantial overlap, and said substantially linear edges thereof being closely spaced and generally parallel; at least one additional insulated gate semiconductor switching device disposed in said chamber in close proximity to both of said substantially linear edges of said third and fourth plate-like terminal members; means for interconnecting said substantially linear edge of said third plate-like terminal member to an input of said third plate-like terminal member to an input of said additional semiconductor switching device, whereby input current to said semiconductor switching device can pass through said third plate-like terminal member at a third inductance; and means for interconnecting said substantially linear edge of said fourth plate-like terminal member to an output of said semiconductor switching device, whereby output current from said semiconductor switching device can pass through said fourth plate-like terminal member at a magnitude substantially equal to that of said input current and at an inductance generally similar to said third inductance; effective to form a second switch in which respective current flow inductance in said third and fourth plate-like terminal members substantially negate one another.

Claim 7

The module of claim 5 wherein the first and second switches have similar impedances.

Claim 8

The module of claim 5 wherein the first and third plate-like terminal members are substantially coplanar, and their edges opposite from their substantially linear edges are at least partly mutually complementary in configuration.

Claim 9

The module of claim 5 wherein the first and third plate-like terminal members are substantially coplanar, and their edges opposite from their substantially linear edges are at least partly mutually complementary in configuration, the second and fourth plate-like terminal members are substantially coplanar, and their edges opposite from their substantially linear edges are at least partly mutually complementary in configuration, and only partially overlap the first and third opposite edges, effective to allow a line of terminals to contact said plate-like terminal members.

Claim 10

The module of claim 8 wherein one of said terminals in said line of terminals contacts the first plate-like terminal member, a second terminal contacts the second and third plate-like terminal members and a third terminal contacts the fourth plate-like terminal member.

Claim 11

The module of claim 9 wherein said terminals are consecutive terminals in said line of terminals.

Claim 12

The module of claim 1 that further includes a first dielectric spacer layer between said first plate-like terminal member and said baseplate, a second dielectric spacing layer between said first and second plate-like terminal members, and one of said first and second spacing layers contains a gate conductor for low electrical resistance connection to a gate electrode on said at least one insulated gate semiconductor switching device.

Claim 13

The module of claim 1 wherein the at least one insulated gate switching device is an insulated gate bipolar transistor.

Claim 14

The module of claim 5 wherein the at least one insulated gate switching device is an insulated gate bipolar transistor.

Claim 15

The module of claim 11 wherein the at least one insulated gate switching device is an insulated gate bipolar transistor.

Claim 16

The module of claim 1 wherein the chamber includes a first plurality of the at least one insulated gate semiconductor switching devices, and the switching devices are symmetrically linearly arrayed substantially parallel to and adjacent to the substantially linear edge of one of the first and second plate-like terminal members.

Claim 17

The module of claim 5 wherein the chamber includes first and second plurality of the at least one insulated gate semiconductor switching devices, one plurality of such switching devices is symmetrically linearly arrayed substantially parallel to and adjacent to the substantially linear edges of the first and second plate-like terminal members, and the second plurality of such switching devices is symmetrically linearly arrayed substantially parallel to and adjacent to the substantially linear edges of the third and fourth plate-like terminal members.

Claim 18

The module of claim 7 that further includes a first dielectric spacer layer between the housing baseplate and the first and third plate-like terminal members, a second dielectric spacing layer between both the said first and third plate-like terminal members and both the second and fourth plate-like terminal members, and first and second gate conductors in one of said first and second spacing layers for respective low electrical resistance connection to a gate electrode on said at least one insulated gate semiconductor switching device and on said at least one additional insulated gate semiconductor switching device.

Claim 19

The module of claim 17 wherein the chamber includes a first and second plurality of the at least one insulated gate semiconductor switching devices, one plurality of such switching devices is symmetrically linearly arrayed substantially parallel to and adjacent to the substantially linear edges of the first and second plate-like terminal members, and the second plurality of such switching devices is symmetrically linearly arrayed substantially parallel to and adjacent to the substantially linear edges of the third and fourth plate-like terminal members.

Claim 20

The module of claim 17 wherein the substantially linear edges of said first and second switches are oppositely disposed and parallel, whereby input and output currents are in opposite directions in said first and second switches.

Claim 21

The module of claim 18 wherein the substantially linear edges of said first and second switches are oppositely disposed and parallel, whereby input and output currents are in opposite directions in said switches.

Claim 22

The module as recited in claim 15 in which each of the plurality of insulated gate semiconductor switching devices is disposed on a separate and discrete insulating substrate.

Claim 23

The module as recited in claim 18 in which each device in both pluralities of insulated gate semiconductor switching devices is an insulated gate bipolar transistor and is disposed on a separate and discrete insulating substrate.

Claim 24

The module of claim 22 in which the insulating substrates are dielectric wafers with opposed faces that are substantially completely metallized, and said metallized wafers are similar in composition and geometry.

Claim 25

The module of claim 1 wherein the housing also includes at least one embedded conductor for low resistance electrical connection to at least one of a gate electrode on the at least one insulated gate semiconductor switching device and the plate-like terminal members.

Claim 26

The module of claim 5 wherein the housing also includes two spaced groups of three embedded conductors, with each group containing a gate conductor, a kelvin emitter conductor, and a kelvin collector conductor.

Claim 27

The module of claim 11 wherein the housing has an embedded gate conductor overlying the gate conductor embedded in one of said spacers, and the gate conductors, the housing and said one spacer have registered apertures, and the registered apertures have a metal pin wedged therein, effective to interconnect the embedded gate conductors.

Claim 28

A high power semiconductor device module capable of operating at high frequency and low parasitic losses comprising; a housing; a housing ring having a bridge-like integral portion extending between two housing sides; a baseplate for said housing and defining a chamber with said housing, said baseplate having a generally planar surface and a given coefficient of expansion and conformations for location of a plastic spacer on said surface; an insulating first plastic spacer on said surface, said spacer having a plurality of conformations thereon for locating the spacer on the baseplate and for locating and spacing a pair of coplanar output terminal plates thereon; a first output terminal plate in said chamber on said first plastic spacer substantially parallel to said baseplate and having a given composition and a given configuration that includes a substantially linear edge for low impedance connection to a first plurality of high power insulated gate bipolar transistors, said first output terminal plate having a given electrical resistance and inductance with respect to electrical current flow therethrough; a second output terminal plate in said chamber on said first plastic spacer substantially parallel to said baseplate and having a given composition and a given configuration that includes a substantially linear edge for low impedance connection to a second plurality of high power insulated gate bipolar transistors, said second output terminal plate being coplanar with said first output terminal plate and having substantially said given electrical resistance and inductance with respect to electrical current flow therethrough; an insulating second plastic spacer on said coplanar terminal plates, said second spacer having a plurality of conformations thereon for locating the second plastic spacer on said first and second output terminal plates and for locating and spacing a pair of coplanar input terminal plates thereon; a first input terminal plate in said chamber on said second plastic spacer, said first input terminal plate having substantially said given composition and configuration that includes a substantially linear edge for low impedance connection to the first plurality of high power insulated gate bipolar transistors, said first input terminal plate located with its linear edge substantially in register with that of said first output terminal plate and in substantial overlap therewith, said first input terminal plate substantially having said given electrical resistance and inductance with respect to electrical current flow therethrough; a second input terminal plate in said chamber on said second plastic spacer, said second input terminal plate having substantially said given composition and configuration that includes a substantially linear edge for low impedance connection to the second plurality of high power insulated gate bipolar transistors, said second input terminal plate located with its linear edge substantially in register with that of said second output terminal plate and in substantial overlap therewith, said second input terminal plate substantially having said given electrical resistance and inductance with respect to electrical current flow therethrough; each of said coplanar terminal plates having an edge opposite from its linear edge that faces the other plate and is at least partly complementary in shape to that of the other plate, effective to provide substantial nesting of the facing edges and substantially parallel linear edges thereon, whereby substantial overlapping of all terminal plates is present but leaves sufficient inner terminal plate area not overlapped to make contact with a line of terminals, whereby input and output current in the first input and output terminal plates is substantially equal but opposite in direction, effective for the inductance of one to substantially cancel the inductance of the other; a first linear group of high voltage and high current insulated gate bipolar transistors in said chamber symmetrically and closely parallelly disposed with respect to the linear edge of the first input and output terminal plates; a second linear group of high voltage and high current insulated gate bipolar transistors in said chamber symmetrically and closely parallelly disposed with respect to the linear edge of the second input and output terminal plates; the first and second transistor groups being parallel to each other, being similarly disposed on opposite sides of the overlapping terminal plates, and the transistors in each group having substantially equal electrical performance characteristics; input and output electrical connections between said first and second transistor groups and their respective first and second input and output terminal plates, each such connection being essentially the same impedance as the others, and thereby providing symmetry in input and output connection resistance and inductance; at least a portion of the input and output connections for each insulated gate bipolar transistor being in substantially parallel disposition to each other at least in one plane, and in close enough proximity to help reduce net electrical inductance of said connections; two gate conductor means in said chamber, each having a first portion disposed within said chamber and adapted to supply substantially equal gate voltage to each of said insulated gate bipolar transistors, and further having a terminal portion disposed outside said chamber for low electrical resistance mechanical connection to a source of gate control voltage; and gate electrical connections of substantially the same composition and impedance between each of said insulated gate bipolar transistors and said gate conductor means; effective to provide a high power semiconductor device module operable at high frequency but having minimized inductance and capable of operating all of said insulated gate bipolar transistors at substantially identical operating levels.

Claim 29

A high power semiconductor device module capable of operating at high frequency and low parasitic losses comprising; a housing; a housing ring having a bridge-like integral portion extending between two housing sides; a baseplate for said housing and defining a chamber with said housing, said baseplate having a generally planar surface and a given coefficient of expansion and conformations for location of a plastic spacer on said surface; an insulating first plastic spacer on said surface, said spacer having a plurality of conformations thereon for locating the spacer on the baseplate and for locating and spacing a pair of coplanar output terminal plates thereon; a first output terminal plate in said chamber on said first plastic spacer substantially parallel to said baseplate and having a given composition and a given configuration that includes a substantially linear edge for low impedance connection to a first plurality of high power insulated gate bipolar transistors, said first output terminal plate having a given electrical resistance and inductance with respect to electrical current flow therethrough; a second output terminal plate in said chamber on said first plastic spacer substantially parallel to said baseplate and having a given composition and a given configuration that includes a substantially linear edge for low impedance connection to a second plurality of high power insulated gate bipolar transistors, said second output terminal plate being coplanar with said first output terminal plate and having substantially said given electrical resistance and inductance with respect to electrical current flow therethrough; an insulating second plastic spacer on said coplanar terminal plates, said second spacer having a plurality of conformations thereon for locating the second plastic spacer on said first and second output terminal plates and for locating and spacing a pair of coplanar input terminal plates thereon; a first input terminal plate in said chamber on said second plastic spacer, said first input terminal plate having substantially said given composition and configuration that includes a substantially linear edge for low impedance connection to the first plurality of high power insulated gate bipolar transistors, said first input terminal plate located with its linear edge substantially in register with that of said first output terminal plate and in substantial overlap therewith, said first input terminal plate substantially having said given electrical resistance and inductance with respect to electrical current flow therethrough; a second input terminal plate in said chamber on said second plastic spacer, said second input terminal plate having substantially said given composition and configuration that includes a substantially linear edge for low impedance connection to the second plurality of high power insulated gate bipolar transistors, said second input terminal plate located with its linear edge substantially in register with that of said second output terminal plate and in substantial overlap therewith, said second input terminal plate substantially having said given electrical resistance and inductance with respect to electrical current flow therethrough; each of said coplanar terminal plates having an edge opposite from its linear edge that faces the other plate and is at least partly complementary in shape to that of the other plate, effective to provide substantial nesting of the facing edges and substantially parallel linear edges thereon, whereby substantial overlapping of all terminal plates is present but leaves sufficient inner terminal plate area not overlapped to make contact with a line of terminals, whereby input and output current in the first input and output terminal plates is substantially equal but opposite in direction, effective for the inductance of one to substantially cancel the inductance of the other; a first linear group of high voltage and high current insulated gate bipolar transistors in said chamber symmetrically and closely parallelly disposed with respect to the linear edge of the first input and output terminal plates; a second linear group of high voltage and high current insulated gate bipolar transistors in said chamber symmetrically and closely parallelly disposed with respect to the linear edge of the second input and output terminal plates; the first and second transistor groups being parallel to each other, being similarly disposed on opposite sides of the overlapping terminal plates, and the transistors in each group having substantially equal electrical performance characteristics; input and output electrical connections between said first and second transistor groups and their respective first and second input and output terminal plates, each such connection being essentially the same impedance as the others, and thereby providing symmetry in input and output connection resistance and inductance; at least a portion of the input and output connections for each insulated gate bipolar transistor being in substantially parallel disposition to each other at least in one plane, and in close enough proximity to help reduce net electrical inductance of said connections; two gate conductor means in said chamber, each having a first portion disposed within said chamber and adapted to supply substantially equal gate voltage to each of said insulated gate bipolar transistors, and further having a terminal portion disposed outside said chamber for low electrical resistance mechanical connection to a source of gate control voltage; and gate electrical connections of substantially the same composition and impedance between each of said insulated gate bipolar transistors and said gate conductor means; effective to provide a high power semiconductor device module operable at high frequency but having minimized inductance and capable of operating all of said insulated gate bipolar transistors at substantially identical operating levels.

Claim 30

The high power module of claim 27 wherein at least one of said gate electrical connections and said gate conductor means includes resistor means for equalizing gate voltage supplied to each of said insulated gate bipolar transistors.

Claim 31

The high power module of claim 27 wherein said gate conductor means includes a plurality of resistors that are effective to supply equal gate voltage to all of said insulated gate bipolar transistors.

Claim 32

The high power module of claim 27 in which each of said gate conductor means includes a resistor for each of said transistors, and each of said resistors is beam trimmable, and each has a trimmed value that results in supplying equal gate voltage to all of said transistors.

Claim 33

The module as recited in claim 27 in which each insulated gate bipolar transistor in each group is disposed on a separate and discrete insulating substrate that forms a substrate assembly.

Claim 34

The module of claim 31 in which the insulating substrates are dielectric wafers with opposed faces that are substantially completely metallized, and said metallized wafers are similar in composition and geometry.

Claim 35

The module of claim 27 wherein the module housing has a mounting bolt and the mounting bolt compresses a trapped frusto-conical spring-like washer, effective to maintain a predetermined clamping force between said baseplate of the module and module support.

Claim 36

The module of claim 27 wherein the baseplate has an interior chamber, an inlet to said chamber and an outlet to said chamber, effective to allow a fluid to be passed through said baseplate for cooling the baseplate.

Claim 37

The module of claim 27 wherein the baseplate has a coefficient of expansion similar to that of said substrate subassemblies and at least one coolant passage therein, with an inlet and an outlet to said coolant passage, and a coolant passage extends under substantially the entirety of each group of transistors, effective to cool said substrate subassemblies substantially equally.

Claim 38

The module of claim 27 wherein the housing bridge portion has two generally parallel groups of embedded conductors that each include a gate conductor, the gate conductor in one group overlies a portion of one of the gate conductors embedded in the lower plastic spacer, the gate conductor in the other group overlies a portion of the other gate conductor embedded in the lower plastic spacer, the housing, the gate conductors and the lower plastic spacer have registered apertures, and the registered apertures have a metal pin wedged therein, effective to interconnect the overlying embedded gate conductors.

Claim 39

The module of claim 36 wherein the two groups of embedded conductors also each include an emitter kelvin conductor and a collector kelvin connector, the emitter kelvin conductor overlies a portion of the input conductor for the transistor group connected to the gate conductor of that embedded group, the collector kelvin conductor overlies a portion of the output conductor for the transistor group connected to the gate conductor of that embedded group, said portions having no other conductor between them and said overlying embedded conductor, a first series of registered apertures at least in said housing, said emitter kelvin conductor and said input conductor portion, a second series of registered apertures at least in said housing, said collector kelvin conductor and said output conductor portion, a first pin press-fitted in said first series of apertures and interconnecting said emitter kelvin conductor with said input conductor, and a second pin press-fitted in said second series of apertures and interconnecting said collector kelvin conductor with said output conductor.