Semiconductor memory device and method for fabricating the same dynamic random access memory device construction

Claim 2

A dynamic random access memory (dRAM) device including a matrix of memory cells each constituted by one transistor and one capacitor, comprising: a gate electrode provided at said transistor of each of said memory cells, said gate electrode being formed in a predetermined portion of an insulating layer disposed over a semiconductor substrate, in a buried manner; a trench formed in said semiconductor substrate through a predetermined portion of said insulating layer; and a semiconductor layer having impurity-doped regions formed in a region defined over a transistor gate electrode-buried portion of said insulating layer and a predetermined region defined in said trench; wherein said semiconductor substrate includes a high concentration impurity-doped region and an epitaxial layer formed over said high concentration impurity-doped region.

Claim 3

A dynamic random access memory (dRAM) device including a matrix of memory cells each constituted by one transistor and one capacitor, comprising: a gate electrode provided at said transistor of each of said memory cells, said gate electrode being formed in a predetermined portion of an insulating layer disposed over a semiconductor substrate, in a buried manner; a trench formed in said semiconductor substrate through a predetermined portion of said insulating layer; and a polysilicon layer having impurity-doped regions formed in a region defined over a transistor gate electrode-buried portion of said insulating layer and a predetermined region defined in said trench; wherein said impurity-doped regions are a source and drain of said transistor, and a storage node of said capacitor; and wherein said node is formed by doping impurity ions into a deposited polysilicon.

Claim 4

A dynamic random access memory (dRAM) device including a matrix of memory cells each constituted by one transistor and one capacitor, comprising: a gate electrode provided at said transistor of each of said memory cells, said gate electrode being formed in a predetermined portion of an insulating layer disposed over a semiconductor substrate, in a buried manner; a trench formed in said semiconductor substrate through a predetermined portion of said insulating layer; and a polysilicon layer having impurity-doped regions formed in a region defined over a transistor gate electrode-buried portion of said insulating layer and a predetermined region defined in said trench; wherein said impurity-doped regions are a source and drain of said transistor, and a storage node of said capacitor; and wherein said node is formed by doping impurity ions into a deposited polysilicon.

Claim 5

A dRAM device in accordance with claim 2, wherein adjacent edges of said gate electrode and said drain are vertically aligned.

Claim 6

A dRAM device in accordance with claim 2, wherein said source, said drain and said storage node are formed in a single layer.

Claim 7

A dynamic random access memory (dRAM) device including a matrix of memory cells each constituted by one transistor and one capacitor, comprising: a gate electrode provided at said transistor of each said memory cells, said gate electrode being formed in a predetermined portion of an insulating layer disposed over a semiconductor substrate, in a buried manner; a trench formed in said semiconductor substrate through a predetermined portion of said insulating layer; and a polysilicon layer having impurity-doped regions formed in a region defined over a transistor gate electrode-buried portion of said insulating layer and a predetermined region defined in said trench; wherein a region of said polysilicon layer disposed over said transistor gate electrode forms a transistor channel region; and wherein said semiconductor substrate comprises a high concentration impurity-doped region and an epitaxial layer formed over said high concentration impurity-doped region.

Claim 8

A dynamic random access memory (dRAM) device including a matrix of memory cells each constituted by one transistor and one capacitor, comprising: a gate electrode provided at said transistor of each said memory cells, said gate electrode being formed in a predetermined portion of an insulating layer disposed over a semiconductor substrate, in a buried manner; a trench formed in said semiconductor substrate through a predetermined portion of said insulating layer; and a polysilicon layer having impurity-doped regions formed in a region defined over a transistor gate electrode-buried portion of said insulating layer and a predetermined region defined in said trench; wherein a region of said polysilicon layer disposed over said transistor gate electrode forms a transistor channel region; and wherein said semiconductor substrate comprises a high concentration impurity-doped region and an epitaxial layer formed over said high concentration impurity-doped region.

Claim 9

A dRAM device in accordance with claim 5, wherein said impurity-doped regions are a source and a drain of said transistor, and a storage node of said capacitor.

Claim 10

A dRAM device in accordance with claim 6, wherein adjacent ends of said gate electrode and said drain are not horizontally offset.

Claim 11

A dRAM device in accordance with claim 6, wherein an end of said drain is directly above and in substantially alignment with an end of said gate electrode.

Claim 12

A dynamic random access memory (dRAM) device, comprising: a matrix of memory cells, each including a single transistor and a single capacitor; a semiconductor substrate; an insulating layer disposed over said substrate; a gate electrode at said transistor of each said cell, said electrode being buried in said insulating layer; a trench passing through a portion of said insulating layer and down into said substrate; and a polysilicon layer having impurity-doped regions formed over said gate electrode and a region formed in said trench; wherein said polysilicon layer includes a source and a drain, both above and directly on said insulating layer; and wherein adjacent edges of said gate electrode and said drain are not horizontally offset.

Claim 13

A dynamic random access memory (dRAM) device, comprising: a matrix of memory cells, each including a single transistor and a single capacitor; a semiconductor substrate; an insulating layer disposed over said substrate; a gate electrode at said transistor of each said cell, said electrode being buried in said insulating layer; a trench passing through a portion of said insulating layer and down into said substrate; and a polysilicon layer having impurity-doped regions formed over said gate electrode and a region formed in said trench; wherein said polysilicon layer includes a source and a drain, both above and directly on said insulating layer; and wherein adjacent edges of said gate electrode and said drain are not horizontally offset.

Claim 14

A dRAM device in accordance with claim 9, wherein said insulating layer is formed on an epitaxial silicon layer.

Claim 15

A dRAM device in accordance with claim 9, wherein said impurity-doped regions are a source and a drain for said transistor, and a storage node of said capacitor.

Claim 16

A dRAM device in accordance with claim 11, wherein said node is formed by doping impurity ions into a deposited polysilicon.

Claim 17

A dRAM device in accordance with claim 9, further comprising a gate insulating film on said gate electrode.

Claim 18

A dRAM device in accordance with claim 13, wherein said gate insulating film is deposited directly on said gate electrode with said gate electrode buried in said insulating layer.

Claim 19

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode form in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein said source region, said drain region, said channel region and said storage node are formed in a single layer.

Claim 20

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode form in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein said source region, said drain region, said channel region and said storage node are formed in a single layer.

Claim 21

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein said substrate region and said storage node with said first dielectric film interposed therebetween constitute a first capacitor, and said storage node and said plate electrode with said second dielectric film interposed therebetween constitute a second capacitor, thereby providing a capacitor structure comprised of said first and second capacitors which are connected with each other in parallel and have said storage node in common.

Claim 22

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein said substrate region and said storage node with said first dielectric film interposed therebetween constitute a first capacitor, and said storage node and said plate electrode with said second dielectric film interposed therebetween constitute a second capacitor, thereby providing a capacitor structure comprised of said first and second capacitors which are connected with each other in parallel and have said storage node in common.

Claim 23

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a predetermined portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a region over said insulating layer; a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; and a bit line connected to said drain region through a contact hole formed in a portion of an insulating layer formed over both said transistor and said capacitor.

Claim 24

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a predetermined portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a region over said insulating layer; a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; and a bit line connected to said drain region through a contact hole formed in a portion of an insulating layer formed over both said transistor and said capacitor.

Claim 25

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a predetermined region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein said node is formed by doping impurity ions into a deposited polysilicon.

Claim 26

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a predetermined region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein said node is formed by doping impurity ions into a deposited polysilicon.

Claim 27

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and .said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a predetermined region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein adjacent edges of said gate electrode and said drain region are vertically aligned.

Claim 28

A dynamic random access memory (dRAM) device, comprising: a high concentration substrate region of a first conductivity type; an epitaxial layer of the first conductivity type formed over said substrate region; an insulating layer formed over said epitaxial layer; a transistor gate electrode formed in a buried manner in a portion of said insulating layer; a trench formed in said epitaxial layer and .said substrate region through a portion of said insulating layer; a source region formed over one side portion of said gate electrode and said trench; a drain region formed over the other side portion of said gate electrode; a transistor channel region of a second conductivity type formed over said gate electrode with a gate insulating film interposed therebetween; a capacitor storage node formed on said trench with a first dielectric film interposed therebetween, said capacitor storage node having one portion disposed in said trench below said source region and the other portion extending from said one portion to a predetermined region over said insulating layer; and a capacitor plate electrode formed over said capacitor storage node via a second dielectric film; wherein adjacent edges of said gate electrode and said drain region are vertically aligned.