Gain enhancement technique for operational amplifiers

Claim 2

An operational amplifier circuit having improved common-mode rejection comprising: a differential input section having an input pair for receiving a differential input signal and having a differential output pair including first and second differential outputs; a cascode current source section having a differential input pair coupled to the differential output pair of the input section, a first cascode current source coupled to a first output of the operational amplifier and a second cascode current source coupled to a second output of the operational amplifier; and a cascode current mirror section having a first mirror current source coupled to the first output of the operational amplifier circuit and a second mirror current source coupled to the second output of the operational amplifier circuit, the first mirror current source having a feedback node and a control node and the second mirror current source having a feedback node and a control node, and a fully-differential operational amplifier having a negative input coupled to the first mirror current source feedback node, a positive input coupled to the second mirror current source feedback node, a positive output coupled to the first mirror current source control node, and a negative output coupled to the second mirror current source control node, wherein the fully-differential amplifier is constructed and arranged to amplify a differential feedback signal appearing on the feedback nodes of the first and second mirror current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition.

Claim 3

An operational amplifier circuit according to claim I wherein the first mirror current source comprise;s: a first transistor having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a first bias voltage, and a drain coupled to the first mirror current source feedback node; and a second transistor having a source coupled to the drain of the first transistor, a gate coupled to the first mirror current source control node, and a drain coupled to the first output of the operational amplifier.

Claim 4

An operational amplifier circuit according to claim 2 wherein the first and second transistors are P-channel field-effect-transistors (FET).

Claim 5

An operational amplifier circuit according to claim 1 wherein the second mirror current source comprises: a first transistor having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a first bias voltage, and a drain coupled to the second mirror current source feedback node; and a second transistor having a source coupled to the drain of the first transistor, a gate coupled to the second mirror current source control node, and a drain coupled to the second output of the operational amplifier.

Claim 6

An operational amplifier circuit according to claim 4 wherein the first and second transistors are P-channel field-effect-transistors (FET).

Claim 7

An operational amplifier circuit according to claim 1 wherein the first cascode current source includes a feedback node coupled to the first differential output of the input section and a control node; and wherein the second cascode current source includes a feedback node coupled to the second differential output of the input section and a control node; and wherein the cascode current source section further includes: a second fully-differential operational amplifier having a negative input coupled to the first cascode current source feedback node, a positive input coupled to the second cascode current source feedback node, a positive output coupled to the first cascode current source control node, and a negative output coupled to the second cascode current source control node, wherein the second fully-differential amplifier is constructed and arranged to amplifiy a differential feedback signal appearing on the feedback nodes of the first and second cascode current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition.

Claim 8

An operational amplifier circuit having improved common-mode rejection comprising: a differential input section including a differential input pair for receiving a differential input signal and a differential output pair including first and second differential outputs; a cascode current mirror section having a first mirror current source coupled to it first output of the operational amplifier circuit and a second mirror current source coupled to a second output of the operational amplifier circuit; and a cascode current source section having a first cascode current source coupled to the first output of the operational amplifier circuit and a second cascode current source coupled to the second output of the operational amplifier circuit, the first cascode current source having a feedback node coupled to the second differential output of the input section and having a control node, the second cascode current source having a feedback node coupled to the first differential output of the input section and having a control node, and a fully-differential operational amplifier having a negative input coupled to the first cascode current source feedback node, a positive input coupled to the second cascode current source feedback node, a positive output coupled to the first cascode current source control node, and a negative output coupled to the second cascode current source control node, wherein the second fully-differential amplifier is constructed and arranged to amplify a differential feedback signal appearing on the feedback nodes of the first and second cascode current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition.

Claim 9

An operational amplifier circuit having improved common-mode rejection comprising: a differential input section including a differential input pair for receiving a differential input signal and a differential output pair including first and second differential outputs; a cascode current mirror section having a first mirror current source coupled to it first output of the operational amplifier circuit and a second mirror current source coupled to a second output of the operational amplifier circuit; and a cascode current source section having a first cascode current source coupled to the first output of the operational amplifier circuit and a second cascode current source coupled to the second output of the operational amplifier circuit, the first cascode current source having a feedback node coupled to the second differential output of the input section and having a control node, the second cascode current source having a feedback node coupled to the first differential output of the input section and having a control node, and a fully-differential operational amplifier having a negative input coupled to the first cascode current source feedback node, a positive input coupled to the second cascode current source feedback node, a positive output coupled to the first cascode current source control node, and a negative output coupled to the second cascode current source control node, wherein the second fully-differential amplifier is constructed and arranged to amplify a differential feedback signal appearing on the feedback nodes of the first and second cascode current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition.

Claim 10

An operational amplifier circuit according to claim 7 wherein the first cascode current source comprises: a first transistor having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a bias voltage, and a drain coupled to the first cascode current source feedback node; and a second transistor having a source coupled to the drain of the first transistor, a gate coupled to the first cascode current source control node, and a drain coupled .to the first output of the operational amplifier.

Claim 11

An operational amplifier circuit according to claim 8 wherein the first and second transistors are N-channel field-effect-transistors (FET).

Claim 12

An operational amplifier circuit according to claim 7 wherein the second cascode current source comprises: a first transistor having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a third bias voltage, and a drain coupled to the second cascode current source feedback node; and a second transistor having a source coupled to the drain of the first transistor, a gate coupled to the second cascode current source control node, and a drain coupled to the second output of the operational amplifier.

Claim 13

An operational amplifier circuit according to claim 10 wherein the first and second transistors are N-channel field-effect-transistors (FET).

Claim 14

An operational amplifier circuit according to claim 7 wherein the differential input section comprises: a biasing current source having an output for supplying bias current; a first input transistor having a source coupled to the biasing current source output, a drain coupled to a first differential input of the cascode current source, and a gate coupled to an input terminal of the input pair for receiving a first differential input signal; and a second input transistor having a source coupled to the biasing current source output, a drain coupled to a second differential input of the cascode current source, and a gate coupled to a second input terminal of the input pair for receiving a second differential input signal.

Claim 15

An operational amplifier circuit according to claim 12 wherein the biasing current source comprises: a first transistor having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a first bias voltage, and a drain; and a second transistor having a source coupled to the drain of the first transistor, a gate coupled to a terminal for receiving a second bias voltage, and a drain coupled to the biasing current source output.

Claim 16

An operational amplifier circuit having improved common-mode rejection comprising: a differential input section having a differential input pair for receiving a differential input signal and a differential output pair including first and second differential outputs; a cascode current source section having a first cascode current source coupled to the first output of the operational amplifier circuit and a second cascode current source coupled to the second output of the operational amplifier circuit, the first cascode current source having a feedback node coupled to the second differential output of the input section and having a control node, the second cascode current source having a feedback node coupled to the first differential output of the input section and having a control node; and a first fully-differential operational amplifier having a negative input coupled to the first cascode current source feedback node, a positive input coupled to the second cascode current source feedback node, a positive output coupled to the first cascode current source control node, and a negative output coupled to the second cascode current source control node, wherein the first fully-differential amplifier is constructed and arranged to amplify a differential feedback signal appearing on the feedback nodes of the first and second cascode current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition; a cascode current mirror section having a first mirror current source coupled to the first output and a second mirror current source coupled to the second output, the first mirror current source having a feedback node and a control node and the second mirror current source having a feedback node and a control node, and a second fully-differential operational amplifier having a negative input coupled to the first mirror current source feedback node, a positive input coupled to the second mirror current source feedback node, a positive output coupled to the first mirror current source control node, and a negative output coupled to the second mirror current source control node, wherein the second fully-differential amplifier is constructed and arranged to amplify a differential feedback signal appearing on the feedback nodes of the first and second mirror current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition.

Claim 17

An operational amplifier circuit having improved common-mode rejection comprising: a differential input section having a differential input pair for receiving a differential input signal and a differential output pair including first and second differential outputs; a cascode current source section having a first cascode current source coupled to the first output of the operational amplifier circuit and a second cascode current source coupled to the second output of the operational amplifier circuit, the first cascode current source having a feedback node coupled to the second differential output of the input section and having a control node, the second cascode current source having a feedback node coupled to the first differential output of the input section and having a control node; and a first fully-differential operational amplifier having a negative input coupled to the first cascode current source feedback node, a positive input coupled to the second cascode current source feedback node, a positive output coupled to the first cascode current source control node, and a negative output coupled to the second cascode current source control node, wherein the first fully-differential amplifier is constructed and arranged to amplify a differential feedback signal appearing on the feedback nodes of the first and second cascode current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition; a cascode current mirror section having a first mirror current source coupled to the first output and a second mirror current source coupled to the second output, the first mirror current source having a feedback node and a control node and the second mirror current source having a feedback node and a control node, and a second fully-differential operational amplifier having a negative input coupled to the first mirror current source feedback node, a positive input coupled to the second mirror current source feedback node, a positive output coupled to the first mirror current source control node, and a negative output coupled to the second mirror current source control node, wherein the second fully-differential amplifier is constructed and arranged to amplify a differential feedback signal appearing on the feedback nodes of the first and second mirror current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon when said operational amplified circuit is in operative condition.

Claim 18

An operational amplifier circuit according to claim 14 wherein the differential input section comprises a P-channel input section including P-channel field-effect-transistors (FET), the P-channel input section having It P-channel differential input pair coupled to the differential input pair of the input section for receiving the differential input signal and having a P-channel differential output pair coupled to the cascode current source.

Claim 19

An operational amplifier circuit according to claim 14 wherein the cascode current source section comprises: a first N-channel FET having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a third bias voltage, and a drain coupled to the first cascode current source feedback node; a second N-channel FET having a source coupled to the drain of the first transistor, a gate coupled to the first cascode current source control node, and a drain coupled to the first output of the operational amplifier; a third N-channel FET having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a third bias voltage, and a drain coupled to the second cascode current source feedback node; and a fourth N-channel FET having a source coupled to the drain of the first transistor, a gate coupled to the second cascode current source control node, and a drain coupled to the second output of the operational amplifier.

Claim 20

An operational amplifier circuit according to claim 14 wherein the cascode current mirror section comprises: a first P-channel FET having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a first bias voltage, and a drain coupled to the first mirror current source feedback node; a second P-channel FET having a source coupled to the drain of the first transistor, a gate coupled to the first mirror current source control node, and a drain coupled to the first output of the operational amplifier; a third P-channel FET having a source coupled to a terminal for receiving a supply voltage, a gate coupled to a terminal for receiving a first bias voltage, and a drain coupled to the second mirror current source feedback node; and a fourth P-channel FET having a source coupled to the drain of the first transistor, a gate coupled to the second mirror current source control node, and a drain coupled to the second output of the operational amplifier.

Claim 21

An operational amplifier circuit having improved common-mode rejection comprising: a differential input section having a differential input pair for receiving a differential input signal and a differential output pair including first and second differential outputs. a cascode current source section having a first cascode current source coupled to the first output of the operational amplifier circuit and a second cascode current source coupled to the second output of the operational amplifier circuit, the first cascode current source having a feedback node coupled to the second differential output of the input section and having a control node, the second cascode current source having a feedback node coupled to the first differential output of the input section and having a control node, and a first fully-differential operational amplifier having a negative input coupled to the first cascode current source feedback node, a positive input coupled to the second cascode current source feedback node, a positive output coupled to the first cascode current source control node, and a negative output coupled to the second cascode current source control node, wherein the first fully-differential amplifier amplifies a differential feedback signal appearing on the feedback nodes of the first and second cascode current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon; and a cascode current mirror section having a first mirror current source coupled to the first output and a second mirror current source coupled to the second output, the first mirror current source having a feedback node and a control node and the second mirror Current source having a feedback node and a control node, and a second fully-differential operational amplifier having a negative input coupled to the first mirror current source feedback node, a positive input coupled to the second mirror current source feedback node, a positive output coupled to the first mirror current source control node, and a negative output coupled to the second mirror current source control node, wherein the second fully-differential amplifier amplifies a differential feedback signal appearing on the feedback nodes of the first and second mirror current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon: wherein the differential input section includes a P-channel input section including P-channel field-effect-transistors (FET), the P-channel input section having a P-channel differential input pair coupled to the differential input pair of the input section for receiving the differential input signal and having a P-channel differential output pair coupled to the cascode current source, and wherein the differential input section further includes an N-channel input section including N-channel field-effect-transistors (FET) having an N-channel differential input pair coupled to the differential input pair of the P-channel input section and having an N-channel differential output pair coupled to the cascode current mirror section.

Claim 22

An operational amplifier circuit having improved common-mode rejection comprising: a differential input section having a differential input pair for receiving a differential input signal and a differential output pair including first and second differential outputs. a cascode current source section having a first cascode current source coupled to the first output of the operational amplifier circuit and a second cascode current source coupled to the second output of the operational amplifier circuit, the first cascode current source having a feedback node coupled to the second differential output of the input section and having a control node, the second cascode current source having a feedback node coupled to the first differential output of the input section and having a control node, and a first fully-differential operational amplifier having a negative input coupled to the first cascode current source feedback node, a positive input coupled to the second cascode current source feedback node, a positive output coupled to the first cascode current source control node, and a negative output coupled to the second cascode current source control node, wherein the first fully-differential amplifier amplifies a differential feedback signal appearing on the feedback nodes of the first and second cascode current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon; and a cascode current mirror section having a first mirror current source coupled to the first output and a second mirror current source coupled to the second output, the first mirror current source having a feedback node and a control node and the second mirror Current source having a feedback node and a control node, and a second fully-differential operational amplifier having a negative input coupled to the first mirror current source feedback node, a positive input coupled to the second mirror current source feedback node, a positive output coupled to the first mirror current source control node, and a negative output coupled to the second mirror current source control node, wherein the second fully-differential amplifier amplifies a differential feedback signal appearing on the feedback nodes of the first and second mirror current sources while remaining substantially unresponsive to a common-mode feedback signal appearing thereon: wherein the differential input section includes a P-channel input section including P-channel field-effect-transistors (FET), the P-channel input section having a P-channel differential input pair coupled to the differential input pair of the input section for receiving the differential input signal and having a P-channel differential output pair coupled to the cascode current source, and wherein the differential input section further includes an N-channel input section including N-channel field-effect-transistors (FET) having an N-channel differential input pair coupled to the differential input pair of the P-channel input section and having an N-channel differential output pair coupled to the cascode current mirror section.