Operational amplifier circuit

Claim 1

An operational amplifier characterized by comprising a first potential terminal (V DD ), a second potential terminal (V SS ), a signal input terminal (11, 12), a signal output terminal (33), first, second, third and fourth circuit points (23, 62, 66, 69), amplifying means (10) for amplifying an input signal applied through said signal input terminal (11, 12) and producing the amplified signal at the output terminal, level shift means (20) for shifting the level of the signal output from said amplifying means (10), output means (30) for receiving the output signals from said amplifying means (10) and from said level shift means (20) and producing an output signal as specified by said input signals, and bias means (60) for applying a bias voltage to said level shift means (20), said operational amplifier in which said level shift means (20) includes a first MOS transistor (21) of a first channel type in which the current path is connected between said first potential terminal (V DD ) and said first circuit point (23) and the gate is connected to said output terminal of said amplifying means (10), and a second MOS transistor (22) of said first channel type in which the current path is inserted between said second potential terminal (Vss) and said first circuit point (23); said output means (30) includes a third MOS transistor (31) of said second channel type in which the current path is inserted between said second potential terminal (V SS ) and said output terminal (33) and the gate is connected to said output terminal of said amplifying means (10), and a fourth M O S transistor (32) of said first channel type in which the current path is inserted between said signal output terminal (33) and said second potential terminal (V SS ) and the gate is connected to said first circuit point (23), and said bias means (60) includes a fifth MOS transistor (61) of said second channel type in which the current path is inserted between said first potential terminal (V DD ) and said second circuit point (62) and the gate is connected to said second circuit point (62), a first constant current source (63, 64) inserted between said second circuit point (62) and said second potential terminal ( VSS ), a sixth MOS transistor (65) of said first channel type in which the current path is inserted between said first potential terminal (V DD ) and said third circuit point (66) and the gate is connected to. said second circuit point (62), a seventh MOS transistor (67) of said first channel type in which the current path is inserted between said third circuit point (66) and said second potential terminal (V ss ), a second constant current source (68, 70) inserted between said first potential terminal (V DD ) and said fourth circuit point (69), an eighth MOS transistor (71) of said first channel type in which the current path is inserted between said fourth circuit point (69) and said second potential terminal (V ss ) and the gate is connected to said fourth circuit point (69), and an amplifying section (72) which is connected at a non-inverting input terminal (+) to said third circuit point (66), at the inverting input terminal (-) to said fourth circuit point (69), and at the output terminal to the gates of said second and seventh MOS transistors (22, 67).