Work station and method for transferring data between an external bus and a memory unit

Claim 2

A work station comprising: a central processing unit (CPU); a memory unit; a first interface circuit connected between an external bus and said CPU, said external bus being connected to a device which controls an asynchronous transfer of a starting address and consecutive data elements to said external bus, said first interface circuit enabling data transfer between said external bus and said memory unit; a system clock providing a timing signal to said CPU and said first interface circuit, said timing signal defining consecutive time slots, each time slot equal to a single clock cycle; and a local bus connecting said interface circuit, CPU and memory unit; wherein said local bus includes a control line group for controlling the transfer, over said local bus, of the starting address in a first time slot and consecutive data elements in consecutive time slots; a plurality of additional first interface circuits connected respectively between a plurality of microchannel busses and said local bus; and a plurality of second interface circuits connected respectively between a plurality of memories and said local bus; wherein each of said first and second interface circuits is designed as a self-contained functional block formed as an integrated circuit chip; and said local bus including lines connecting each of said plurality of first and second interface circuits with an arbitrator, respective lines transmitting a local bus access request from respective interface circuits to said arbitrator, and other lines transmitting a local bus granting signal from the arbitrator to a selected one of said plurality of interface circuits.

Claim 3

A work station comprising: a central processing unit (CPU); a memory connected to a memory interface circuit; a device connected to a microchannel bus for controlling asynchronous transfer of an address and consecutive data elements to said microchannel bus; a bus interface circuit, connected between said microchannel bus and CPU, enabling data transfer between said device and said memory unit; a system clock providing a timing signal to said CPU and first interface circuit, said timing signal defining consecutive time slots, each time slot equal to a single clock cycle; and a local bus connecting said interface circuits, CPU and memory unit; wherein said local bus includes a control line group for controlling the transfer, over said local bus, of a starting address in a first time slot and consecutive data elements in consecutive time slots, said control line group including: a BURST line for presenting a BURST signal generated by said bus interface circuit as a bus master and received by said memory interface circuit as a slave indicating a continuous data transfer (burst mode) to follow; a LOCK line for locking said local bus for said continuous data transfer for the duration of the burst mode; an EADS line for transmitting a signal from said first interface circuit to said CPU indicating a burst mode data transfer between said bus interface circuit and said memory interface circuit and adapted to invalidate any data contained in a cache memory of said CPU; wherein an active to inactive transition of said BURST signal temporarily halts a transfer of data in the burst mode whilst maintaining a communication between said bus master and said slave; and a multiplexer/demultiplexer connected on one side to said bus interface circuit and on the other side to both an address line group and a data line group of said local bus; a control line extending between said bus interface circuit and said multiplexer/demultiplexer; wherein said multiplexer/demultiplexer is switched from said address line group to said data line group under control of said bus interface circuit through said control line.

Claim 4

A work station comprising: a central processing unit (CPU); a memory connected to a memory interface circuit; a device connected to a microchannel bus for controlling asynchronous transfer of an address and consecutive data elements to said microchannel bus; a bus interface circuit, connected between said microchannel bus and CPU, enabling data transfer between said device and said memory unit; a system clock providing a timing signal to said CPU and first interface circuit, said timing signal defining consecutive time slots, each time slot equal to a single clock cycle; and a local bus connecting said interface circuits, CPU and memory unit; wherein said local bus includes a control line group for controlling the transfer, over said local bus, of a starting address in a first time slot and consecutive data elements in consecutive time slots, said control line group including: a BURST line for presenting a BURST signal generated by said bus interface circuit as a bus master and received by said memory interface circuit as a slave indicating a continuous data transfer (burst mode) to follow; a LOCK line for locking said local bus for said continuous data transfer for the duration of the burst mode; an EADS line for transmitting a signal from said first interface circuit to said CPU indicating a burst mode data transfer between said bus interface circuit and said memory interface circuit and adapted to invalidate any data contained in a cache memory of said CPU; wherein an active to inactive transition of said BURST signal temporarily halts a transfer of data in the burst mode whilst maintaining a communication between said bus master and said slave; and a multiplexer/demultiplexer connected on one side to said bus interface circuit and on the other side to both an address line group and a data line group of said local bus; a control line extending between said bus interface circuit and said multiplexer/demultiplexer; wherein said multiplexer/demultiplexer is switched from said address line group to said data line group under control of said bus interface circuit through said control line.

Claim 5

The work station of claim 2 further comprising: a plurality of bus interface circuits connected respectively between a plurality of microchannel busses and said local bus; and a plurality of memory interface circuits connected respectively between a plurality of memories and said local bus; wherein each of said bus and memory interface circuits is designed as a self-contained functional block formed as an integrated circuit chip; and wherein said local bus includes lines connecting each of said plurality of bus and memory interface circuits with an arbitrator, respective lines transmitting a local bus access request from respective interface circuits to said arbitrator, and other lines transmitting a local bus granting signal from the arbitrator to a selected one of said plurality of interface circuits.

Claim 6

A work station comprising: a central processing unit (CPU); a memory unit; a first interface circuit connected between an external bus and said CPU, said external bus being connected to a device which controls an asynchronous transfer of a starting address and consecutive data elements to said external bus, said first interface circuit enabling data transfer between said external bus and said memory unit, said interface circuit being designed as a self-contained functional block formed as an integrated circuit chip and provided with a predetermined number of connecting pins, a group thereof being assigned for communicating either addresses or data; a system clock providing a timing signal to said CPU and said first interface circuit, said timing signal defining consecutive time slots, each time slot equal to a single clock cycle; a local bus connecting said interface circuit, CPU and memory unit said local bus including a control line group for controlling the transfer, over said local bus, of the starting address in a first time slot and consecutive data elements in consecutive time slots; said local bus further including both an address line group and a data line group each corresponding in number to said group of connecting pins of said interface circuit and a multiplexer/demultiplexer connected on one side to said group of pins of said interface circuit and on the other side to both said address line group and said data line group.

Claim 7

A work station comprising: a central processing unit (CPU); a memory unit; a first interface circuit connected between an external bus and said CPU, said external bus being connected to a device which controls an asynchronous transfer of a starting address and consecutive data elements to said external bus, said first interface circuit enabling data transfer between said external bus and said memory unit, said interface circuit being designed as a self-contained functional block formed as an integrated circuit chip and provided with a predetermined number of connecting pins, a group thereof being assigned for communicating either addresses or data; a system clock providing a timing signal to said CPU and said first interface circuit, said timing signal defining consecutive time slots, each time slot equal to a single clock cycle; a local bus connecting said interface circuit, CPU and memory unit said local bus including a control line group for controlling the transfer, over said local bus, of the starting address in a first time slot and consecutive data elements in consecutive time slots; said local bus further including both an address line group and a data line group each corresponding in number to said group of connecting pins of said interface circuit and a multiplexer/demultiplexer connected on one side to said group of pins of said interface circuit and on the other side to both said address line group and said data line group.

Claim 8

The work station of claim 4 further comprising: a control line extending between said interface circuit and multiplexer/demultiplexer; wherein said multiplexer/demultiplexer is switched from said address line group to said data line group under control of said interface circuit through said control line.

Claim 9

The work station of claim 4, wherein said local bus includes lines connected between said CPU and first interface circuit for dynamically changing a bus master function from one to the other.

Claim 10

The work station of claim 4 wherein said memory unit includes a memory, and a second interface circuit connected between said local bus and memory.

Claim 11

The work station of claim 7, wherein said control line group includes a BURST line for presenting a BURST signal generated by said first interface circuit as a bus master and received by said second interface circuit as a slave indicating a continuous data transfer (burst mode) to follow.

Claim 12

The work station of claim 8, wherein said control line group further includes a LOCK line for locking said local bus for said continuous data transfer for the duration of the burst mode.

Claim 13

The work station of claim 8, wherein said control line group further includes an EADS line for transmitting a signal from said first interface circuit to said CPU indicating a burst mode data transfer between said first interface circuit and said second interface circuit and adapted to invalidate any data contained in a cache memory of said CPU.

Claim 14

The work station of claim 8, wherein said external bus is a microchannel bus, and wherein an active to inactive transition of said BURST signal temporarily halts a transfer of data in the burst mode whilst maintaining a communication between said bus master and said slave.

Claim 17

The method of claim 12 further comprising: generating a signal indicating the presence of said starting address on said bus.

Claim 18

The method of claim 12 further comprising: removing said BURST signal while maintaining said LOCK signal on said bus to pause said data transfer.

Claim 19

The method of claim 12, wherein said data is provided by said second unit onto the data lines of said local bus, said data being multiplexed to the same ports of said first unit used for presenting said starting address to said local bus.

Claim 20

The method of claim 12 further comprising: providing a BRDY signal on said bus from said second unit indicating said second unit is ready to receive data.

Claim 21

The method of claim 16 further comprising: removing said BRDY signal to pause said data transfer.