US5440747A
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US
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Data processor with control logic for storing operation mode status and associated method
Assignee: Hitachi America Ltd
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Filing: 1993-09-27
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Granted: 1995-08-08
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Expires: 2013-09-27
Abstract
Abstract A data processor that includes an interrupt controller, a condition code register, a condition code stacking register, a data memory with a stacking area, a data processing unit, and an interrupt request decoder. The interrupt controller receives interrupt request signals including a break interrupt request signal and a plurality of standard interrupt request signals. The condition code register stores condition code values including a data processor mode control value. The data processing unit performs data processing operations. The data processing operations are suspended when the data processor mode control value is set to a predefined "sleep mode" value and are enabled when the data processor mode control value is set to a predefined "run mode". The interrupt decoder responds to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy the mode control value stored in the condition code register into the condition code stacking register, (B) second, condition code register control signals to set the mode control value to-the predefined "run mode" value. It responds to a standard interrupt request signal by generating: (A) first, condition code register control signals to set the mode control value to the predefined "run mode" value; and (B), second, condition code register control signals to copy the mode control value stored in the condition code register into the data stacking area.
Inventors
- 👤 Atsushi Kiuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30094; G06F9/30098; G06F9/3012; G06F9/30134; G06F9/30181; G06F9/30189
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
373 words
A data processor comprising: a data processing core unit for performing data processing operations; said data processing core unit including an interrupt controller for receiving interrupt signals, said received interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; said data processing core unit including a condition code register for storing condition code values including a data processor mode control value; said data processing core unit including a condition code stacking register for storing condition code values received from said condition code register; and a data memory including a data stacking area for storing specified data values; said data processing core unit including mode control means coupled to said condition code register for suspending data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "sleep mode" value and for enabling data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "run mode" value; said data processing core unit including an interrupt decoder, coupled to said interrupt controller, for generating condition code register control signals to operate on said data processor mode control value in accordance with each received interrupt request signal; said interrupt decoder including a state machine for responding to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into said condition code stacking register, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; said interrupt decoder state machine responding to a received standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into said data stacking area; said data processing core unit including a condition code controller for setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
Claim 2
Dependent Claim
373 words
A data processor comprising: a data processing core unit for performing data processing operations; said data processing core unit including an interrupt controller for receiving interrupt signals, said received interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; said data processing core unit including a condition code register for storing condition code values including a data processor mode control value; said data processing core unit including a condition code stacking register for storing condition code values received from said condition code register; and a data memory including a data stacking area for storing specified data values; said data processing core unit including mode control means coupled to said condition code register for suspending data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "sleep mode" value and for enabling data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "run mode" value; said data processing core unit including an interrupt decoder, coupled to said interrupt controller, for generating condition code register control signals to operate on said data processor mode control value in accordance with each received interrupt request signal; said interrupt decoder including a state machine for responding to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into said condition code stacking register, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; said interrupt decoder state machine responding to a received standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into said data stacking area; said data processing core unit including a condition code controller for setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
Claim 3
Dependent Claim
122 words
The data processor of claim 1 wherein: said mode control means suspends data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "software standby mode" value; said data processor further includes a direct memory access (DMA) controller for performing data transfer operations, said DMA controller including means for suspending operation of said DMA controller when said data processor mode control value is set to said predefined "software standby mode" value and for enabling data transfer operations by said DMA controller when said data processor mode control value is set to said predefined "run mode" value and when said data processor mode control value is set to said predefined "sleep mode" value.
Claim 4
Dependent Claim
78 words
The data processor of claim 1 wherein: said interrupt decoder further responding to a received break interrupt request signal by generating a first program branching signal while generating said condition code register control signals to copy said data processor mode control value stored in said condition code register into said condition code stacking register; and said data processing core unit including means for executing a predefined break interrupt service routine in response to said first program branching signal.
Claim 5
Dependent Claim
237 words
The data processor of claim 1 further comprising: a first program counter register for storing a first instruction address; a program stacking register for storing an instruction address received from said first program counter register; a second program counter register for storing a second instruction address; said interrupt decoder state machine responding to each received break interrupt request signal by generating control signals to copy said first instruction address from said second program counter register to said program stacking register; said interrupt decoder state machine responding to a predefined break return instruction by generating (A) control signals to copy said first instruction address from said program stacking register to said first program counter register, and (B) condition code register control signals to copy said data processor mode control value stored in said condition code stacking register into said condition code register; said interrupt decoder state machine responding to each received standard interrupt request signal by generating control signals to copy said first instruction address from said second program counter register to said data stacking area; and said interrupt decoder state machine responding to a predefined standard interrupt return instruction by generating (A) control signals to copy said first instruction address from said data stacking area to said first program counter register, and (B) condition code register control signals to copy said data processor mode control value stored in said data stacking area into said condition code register.
Claim 6
Dependent Claim
341 words
A data processor comprising: a data processing core unit for performing data processing operations; said data processing core unit including an interrupt controller for receiving interrupt signals, said received interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; said data processing core unit including a condition code register for storing condition code values including a data processor mode control value; stacking storage for storing specified data values; said data processing core unit including mode control means coupled to said condition code register for suspending data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "sleep mode" value and for enabling data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "run mode" value; said data processing core unit including an interrupt decoder, coupled to said interrupt controller, for generating condition code register control signals to operate on said data processor mode control value in accordance with each received interrupt request signal; said interrupt decoder including a state machine for responding to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into said stacking storage, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; said interrupt decoder state machine responding to a received standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into said stacking storage; said data processing core unit including a condition code controller for setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
Claim 7
Dependent Claim
341 words
A data processor comprising: a data processing core unit for performing data processing operations; said data processing core unit including an interrupt controller for receiving interrupt signals, said received interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; said data processing core unit including a condition code register for storing condition code values including a data processor mode control value; stacking storage for storing specified data values; said data processing core unit including mode control means coupled to said condition code register for suspending data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "sleep mode" value and for enabling data processing operations by said data processing core unit when said data processor mode control value is set to a predefined "run mode" value; said data processing core unit including an interrupt decoder, coupled to said interrupt controller, for generating condition code register control signals to operate on said data processor mode control value in accordance with each received interrupt request signal; said interrupt decoder including a state machine for responding to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into said stacking storage, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; said interrupt decoder state machine responding to a received standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into said stacking storage; said data processing core unit including a condition code controller for setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
Claim 8
Independent Claim
250 words
A method of handling interrupt requests for interrupting a data processor comprising the steps of: receiving interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; storing in a condition code register of said data processor condition code values including a data processor mode control value; suspending data processing operations by said data processor when said data processor mode control value is set to a predefined "sleep mode" value; enabling data processing operations by said data processor when said data processor mode control value is set to a predefined "run mode" value; responding to a break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into a condition code stacking register of said data processor, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; responding to a standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into a data memory of said data processor that includes a data stacking area; and setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
Claim 9
Independent Claim
250 words
A method of handling interrupt requests for interrupting a data processor comprising the steps of: receiving interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; storing in a condition code register of said data processor condition code values including a data processor mode control value; suspending data processing operations by said data processor when said data processor mode control value is set to a predefined "sleep mode" value; enabling data processing operations by said data processor when said data processor mode control value is set to a predefined "run mode" value; responding to a break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into a condition code stacking register of said data processor, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; responding to a standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into a data memory of said data processor that includes a data stacking area; and setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
Claim 10
Dependent Claim
103 words
The method of claim 6 further comprising the steps of: suspending data processing operations by said data processor when said data processor mode control value is set to a predefined "software standby mode" value; suspending data transfer operations by a direct memory access (DMA) controller of said data processor when said data processor mode control value is set to said predefined "software standby mode" value and enabling data transfer operations by said DMA controller when said data processor mode control value is set to a predefined "run mode" and when said data processor mode control value is set to a predefined "sleep mode".
Claim 11
Dependent Claim
69 words
The method of claim 6 further comprising the steps of: responding to a received break interrupt request signal by generating a first program branching signal while generating said condition code register control signals to copy said data processor mode control value stored in said condition code register into said condition code stacking register; and executing a predefined break interrupt service routine in response to said first program branching signal.
Claim 12
Dependent Claim
204 words
The method of claim 6 further comprising the steps of: storing in a first program counter register of said data processor a first instruction address; responding to each received break interrupt request signal by generating control signals to copy said first instruction address from said first program counter register to a program stacking register of said data processor; responding to a predefined break return instruction by generating (A) control signals to copy said first instruction address from said program stacking register to a second program counter register of said data processor, and (B) condition code register control signals to copy said data processor mode control value stored in said condition code stacking register into said condition code register; responding to each received standard interrupt request signal by generating control signals to copy said first instruction address from said first program counter register to said data stacking area; and responding to a predefined standard interrupt return instruction by generating (A) control signals to copy said first instruction address from said data stacking area to said second program counter register, and (B) condition code register control signals to copy said data processor mode control value stored in said data stacking area into said condition code register.
Claim 13
Independent Claim
241 words
A method for handling interrupt requests for interrupting a data processor comprising the steps of: receiving interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; storing in a condition code register of said data processor condition code values including a data processor mode control value; suspending data processing operations by said data processing unit when said data processor mode control value is set to a predefined "sleep mode" value; enabling data processing operations by said data processing unit when said data processor mode control value is set to a predefined "run mode" value; responding to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into a stacking storage of said data processor, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; responding to a standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into said stacking storage; and setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
Claim 14
Independent Claim
241 words
A method for handling interrupt requests for interrupting a data processor comprising the steps of: receiving interrupt signals including a break interrupt request signal and a plurality of standard interrupt request signals; storing in a condition code register of said data processor condition code values including a data processor mode control value; suspending data processing operations by said data processing unit when said data processor mode control value is set to a predefined "sleep mode" value; enabling data processing operations by said data processing unit when said data processor mode control value is set to a predefined "run mode" value; responding to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy said data processor mode control value stored in said condition code register into a stacking storage of said data processor, (B) second, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; responding to a standard interrupt request signal by generating: (A) first, condition code register control signals to set said data processor mode control value to said predefined "run mode" value; and (B), second, condition code register control signals to copy said data processor mode control value stored in said condition code register into said stacking storage; and setting said data processor mode control value and copying said data processor mode control value in accordance with said condition code register control signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |