Patent US5440722A successfully refreshed from Google Patents.
US5440722A
Expired / Lapsed
US
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System bus monitor for compiling data regarding use of a system bus
Assignee: Banyan Systems Inc
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Filing: 1992-07-22
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Granted: 1995-08-08
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Expires: 2012-07-22
Abstract
Abstract A method and apparatus for monitoring electrical signals within a system bus to compile statistics regarding the use of the bus by each of a plurality of circuit boards. The apparatus includes a trace memory for storing samples of the bus's electrical signals. A processor analyzes the samples to detect bus cycles, determines which of the circuit boards initiated the bus cycles, and prepares statistics regarding the use of the system bus by each circuit board. A display system prepares illustrations, such as graphs, which depict selected statistics. The apparatus also includes an application status register for storing information regarding the status of software executed by a processor board. The software sets a bit of the application status register to indicate that a specified event has begun and clears the bit to indicate that the specified event has terminated. The apparatus includes circuitry for reading the application status register to monitor the event.
Inventors
- 👤 Adrian T. VanderSpek
- 👤 Edward A. Bennett
- 👤 Dana M. Richmond
- 👤 Christopher A. Ramos
- 👤 Joseph V. Aurelio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/349; G06F11/3409; G06F11/3419; G06F11/3423; G06F11/348
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
260 words
A system bus monitor for monitoring electrical signals generated by each of a plurality of circuit boards including a network interface circuit board, a central processing unit circuit board and a disk interface/controller circuit board, all of said circuit boards being connected to a system bus, said electrical signals initiating and executing bus cycles on said system bus, the system bus monitor comprising: a sampling means for preparing, for each bus cycle, at least two bus samples representing the status of said electrical signals at time intervals during said bus cycle, a trace memory, connected to said sampling means, for storing said at least two bus samples prepared by said sampling means, cycle detection means, connected to said trace memory, for detecting at least one bus cycle in said at least two bus samples stored by said trace memory, cycle analysis means, connected to said cycle detection means, for analyzing said at least two bus samples of each said bus cycle identified by said cycle detection means to determine which of said plurality of circuit boards initiated said at least one bus cycle, and means for compiling data regarding the use of said system bus by said each of said plurality of circuit boards connected to said system bus, said means for compiling data being connected to said cycle analysis means; means for a user to request the resources to be monitored and specific data of said data regarding use of said system bus that should be compiled, said means for requesting being connected to said means for compiling data.
Claim 2
Independent Claim
260 words
A system bus monitor for monitoring electrical signals generated by each of a plurality of circuit boards including a network interface circuit board, a central processing unit circuit board and a disk interface/controller circuit board, all of said circuit boards being connected to a system bus, said electrical signals initiating and executing bus cycles on said system bus, the system bus monitor comprising: a sampling means for preparing, for each bus cycle, at least two bus samples representing the status of said electrical signals at time intervals during said bus cycle, a trace memory, connected to said sampling means, for storing said at least two bus samples prepared by said sampling means, cycle detection means, connected to said trace memory, for detecting at least one bus cycle in said at least two bus samples stored by said trace memory, cycle analysis means, connected to said cycle detection means, for analyzing said at least two bus samples of each said bus cycle identified by said cycle detection means to determine which of said plurality of circuit boards initiated said at least one bus cycle, and means for compiling data regarding the use of said system bus by said each of said plurality of circuit boards connected to said system bus, said means for compiling data being connected to said cycle analysis means; means for a user to request the resources to be monitored and specific data of said data regarding use of said system bus that should be compiled, said means for requesting being connected to said means for compiling data.
Claim 3
Dependent Claim
33 words
The system bus monitor of claim 1 wherein said means for compiling data comprises means to create bus objects and bucket definition objects for each type of cycle performed by a bus object.
Claim 4
Dependent Claim
60 words
The system bus monitor of claim 1 further comprising: a user interface means for receiving from a user requests for specific data of said data regarding use of said system bus by each of said plurality of circuit boards, and display means connected to said user interface means for displaying said data in response to said requests from a user.
Claim 5
Dependent Claim
33 words
The system bus monitor of claim 3 further comprising means for determining, for each said circuit board, a percentage of bus cycles generated by said circuit board during a specified period of time.
Claim 6
Dependent Claim
122 words
The system bus monitor of claim 1 wherein said plurality of circuit boards includes a board which includes a central processing means for executing software and wherein said system bus monitor further comprises: an application status register, connected to said system bus, for storing information regarding the status of software executed by said central processing means, a user interface means for specifying a software event to be detected by said system bus monitor, said user interface means being connected to a means for detecting said specified software event, said means for detecting being connected to said system bus; and means for setting at least one bit of said application status register upon the occurrence of said specified software event to be detected.
Claim 7
Dependent Claim
50 words
The system bus monitor of claim 5 wherein said central processing means comprises: means for reading said application status register, and means for determining whether said specified event has occurred based on the content of said application status register, said means for determining being connected to said means for reading.
Claim 8
Dependent Claim
43 words
The system bus monitor of claim 5 further comprising means for clearing said at least one bit to indicate that said specified event has terminated and wherein said central processing means includes means for reading said application status register to monitor said event.
Claim 9
Dependent Claim
79 words
The system bus monitor of claim 5 wherein said cycle analysis means further comprises: means for determining a type of each said detected cycle; means for determining a beginning and an end of each said detected cycle; and means for determining the length of time between a beginning and an end of each said detected cycle, said means for determining the length being connected to said means for determining a beginning and an end of each said detected cycle.
Claim 10
Dependent Claim
35 words
The system bus monitor of claim 8 wherein said cycle analysis means further includes, for each of said plurality of circuit boards, means for determining the aggregate length of all cycles initiated by said board.
Claim 11
Independent Claim
71 words
A method of monitoring use of a bus by devices connected to said device comprising the steps of: acquiring raw bus signals from said bus and storing said signals in a buffer memory; parsing the bus signals stored in said buffer memory into bus cycles; grouping statistics relating to said bus cycles into buckets defined by a user of said devices and bus; gathering together all buckets relating to a device.
Claim 12
Independent Claim
71 words
A method of monitoring use of a bus by devices connected to said device comprising the steps of: acquiring raw bus signals from said bus and storing said signals in a buffer memory; parsing the bus signals stored in said buffer memory into bus cycles; grouping statistics relating to said bus cycles into buckets defined by a user of said devices and bus; gathering together all buckets relating to a device.
Claim 13
Dependent Claim
30 words
The method of monitoring the use of a bus of claim 10 further comprising the step of creating a data object for each bus cycle parsed from said bus signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |