US5440550A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed switching architecture
Assignee: Telstra Corp Ltd
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Filing: 1992-07-01
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Granted: 1995-08-08
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Expires: 2012-07-01
Abstract
Abstract The present invention provides a high speed non-blocking buffered banyan packet switching architecture which utilizes parallel switching fabrics to switch slices of serial packets (subpackets) in a parallel manner. Serial digital information is received, converted into parallel form, buffered, and introduced into a parallel interconnect network which provides separate parallel paths for each packet/subpacket of information. The parallel subpackets are multiplexed, switched, demultiplexed, and recombined by way of a parallel-to-serial converter and an output port controller so as to reconstitute the original serial data stream, thereby providing high speed effective data switching at relatively low clock speeds.
Inventors
- 👤 Douglas Follett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:41
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/15; H04L49/1515; H04L49/153; H04L49/1538; H04L49/1553; H04L49/1561; H04L49/25; H04L49/253; H04L49/255; H04L2012/5678; H04L2012/5681
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
124 words
A multistage space division packet switch, comprising a switching fabric unit SFU having a plurality of inputs and a plurality of outputs, each input having an input port controller means and each output having an output port controller means, wherein said input port controller means are adapted to convert each input serial packet into a plurality of parallel subpackets, said SFU including internal parallel switching planes, each of said parallel switching planes comprising a first stage including a first buffer means, a parallel interconnect network, and a second stage comprising at least one buffer means associated with each of a plurality of addressable outputs, and said output port controller means including means for converting said parallel subpackets into a serial packet form for output.
Claim 2
Dependent Claim
124 words
A multistage space division packet switch, comprising a switching fabric unit SFU having a plurality of inputs and a plurality of outputs, each input having an input port controller means and each output having an output port controller means, wherein said input port controller means are adapted to convert each input serial packet into a plurality of parallel subpackets, said SFU including internal parallel switching planes, each of said parallel switching planes comprising a first stage including a first buffer means, a parallel interconnect network, and a second stage comprising at least one buffer means associated with each of a plurality of addressable outputs, and said output port controller means including means for converting said parallel subpackets into a serial packet form for output.
Claim 3
Dependent Claim
13 words
A packet switch according to claim 1, wherein said packets are self addressing.
Claim 4
Dependent Claim
29 words
A packet switch according to claim 1, wherein said internal planes are synchronized such that said parallel subpackets arrive in the correct order at said output port controller means.
Claim 5
Dependent Claim
13 words
A packet switch according to claim 3, wherein said packets are self addressing.
Claim 6
Dependent Claim
13 words
A packet switch comprising a plurality of packet switches according to claim 1.
Claim 7
Independent Claim
126 words
A method of packet switching, in a system comprising a switching fabric unit SFU having a plurality of inputs and a plurality of outputs, each input having an input port controller means and each output having an output port controller means, comprising the steps of: converting each input serial packet into a plurality of parallel subpackets at said input port controller means; inputting each of said plurality of parallel subpackets to one of a set of parallel switching planes in said SFU; switching each of said plurality of parallel subpackets over a set of internal parallel paths within said plane; outputting from said SFU said plurality of parallel subpackets; and reassembling each serial packet from said plurality of parallel subpackets at said output port controller means.
Claim 8
Independent Claim
126 words
A method of packet switching, in a system comprising a switching fabric unit SFU having a plurality of inputs and a plurality of outputs, each input having an input port controller means and each output having an output port controller means, comprising the steps of: converting each input serial packet into a plurality of parallel subpackets at said input port controller means; inputting each of said plurality of parallel subpackets to one of a set of parallel switching planes in said SFU; switching each of said plurality of parallel subpackets over a set of internal parallel paths within said plane; outputting from said SFU said plurality of parallel subpackets; and reassembling each serial packet from said plurality of parallel subpackets at said output port controller means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |