Communication system with redundant links and data bit time multiplexing

Claim 3

A method as claimed in claim 1 wherein the communication channel is reconfigured to bypass an inoperative link with a spare link at the pre-determined position.

Claim 4

The method of claim 1 wherein the transmitting step comprises: in successive cycles: directly transmitting a number of directly transmitted bits of a word over the operating links and storing a number of stored bits of the word for transmission in a succeeding cycle; and in the succeeding cycle, transmitting the previously stored bits with a number of directly transmitted bits of a next succeeding word, the number of directly transmitted bits being less than the number of directly transmitted bits in the prior cycle, and storing a number of stored bits of the next succeeding word for transmission in a later succeeding cycle, the number of stored bits being greater than the number of stored bits in the prior cycle; and after successive cycles, suspending acceptance of a word for a cycle while transmitting all stored bits.

Claim 7

A method as claimed in claim 4 further comprising receiving at a receiver the number of parallel bits of a data word, said receiving comprising holding during a cycle the directly transmitted bits of the data word to bring, during a next succeeding cycle, the directly transmitted bits of the data word into phase with the stored bits of the data word.

Claim 8

A method as claimed in claim 4 further comprising the step of reconfiguring the channel by switches which bypass inoperative communication links.

Claim 11

A communication system for continuing use of a multiple link communication channel as links of the channel become inoperative comprising: a transmitting array of switches and a receiving array of switches, the arrays of switches reconfiguring the communication channel to use less than all the links in the channel by switching an inoperative link toward a pre-determined position; and a bit storage device for storing bits of a data word while remaining bits of the data word are directly transmitted across the channel, such that bits of a data word are transmitted over operating links in a time multiplexed fashion.

Claim 12

A communication system for continuing use of a multiple link communication channel as links of the channel become inoperative comprising: a transmitting array of switches and a receiving array of switches, the arrays of switches reconfiguring the communication channel to use less than all the links in the channel by switching an inoperative link toward a pre-determined position; and a bit storage device for storing bits of a data word while remaining bits of the data word are directly transmitted across the channel, such that bits of a data word are transmitted over operating links in a time multiplexed fashion.

Claim 13

A communication system as claimed in claim 8 wherein the communication channel is reconfigured to bypass an inoperative link with a spare link at the pre-determined position.

Claim 14

A communication system as claimed in claim 8 wherein, to transmit data word in a time multiplexed fashion, the communication system: in successive cycles: directly transmits a number of directly transmitted bits of a word over the operating links and stores a number of stored bits of the word for transmission in a succeeding cycle; and in the succeeding cycle, transmits the previously stored bits with a number of directly transmitted bits of a next succeeding word, the number of directly transmitted bits being less than the number of directly transmitted bits in the prior cycle, and stores a number of stored bits of the next succeeding word for transmission in a later succeeding cycle, the number of stored bits being greater than the number of stored bits in the prior cycle; and after successive cycles, suspends acceptance of a word for a cycle while transmitting all stored bits.

Claim 15

A communication system for communicating a number of parallel bits of data words over a lesser number of communication links of a communication channel comprising: a transmitting subsystem for transmitting bits across the channel; a receiving subsystem for receiving data bits from the channel; and a transmitting subsystem storage device for storing bits of a data word; the communication system in successive cycles: directly transmitting with the transmitting subsystem a number of directly transmitted bits of a word over the communication links and storing with the storage device a number of stored bits of the word for transmission in a succeeding cycle; and in the succeeding cycle, transmitting with the transmitting subsystem the previously stored bits with a number of directly transmitted bit of a next succeeding word, the number of directly transmitted bits being less than the number of directly transmitted bits in the prior cycle, and storing with the storage device a number of stored bits of the next succeeding word for transmission in a later succeeding cycle, the number of stored bits being greater than the number of stored bits in the prior cycle; and after successive cycles, suspending acceptance of a word for a cycle while transmitting all stored bits.

Claim 16

A communication system for communicating a number of parallel bits of data words over a lesser number of communication links of a communication channel comprising: a transmitting subsystem for transmitting bits across the channel; a receiving subsystem for receiving data bits from the channel; and a transmitting subsystem storage device for storing bits of a data word; the communication system in successive cycles: directly transmitting with the transmitting subsystem a number of directly transmitted bits of a word over the communication links and storing with the storage device a number of stored bits of the word for transmission in a succeeding cycle; and in the succeeding cycle, transmitting with the transmitting subsystem the previously stored bits with a number of directly transmitted bit of a next succeeding word, the number of directly transmitted bits being less than the number of directly transmitted bits in the prior cycle, and storing with the storage device a number of stored bits of the next succeeding word for transmission in a later succeeding cycle, the number of stored bits being greater than the number of stored bits in the prior cycle; and after successive cycles, suspending acceptance of a word for a cycle while transmitting all stored bits.

Claim 17

A communication system as claimed in claim 11 further comprising a receiving subsystem storage device for storing directly transmitted bits of a preceding cycle for one cycle to bring the directly transmitted bits of a succeeding cycle into phase with the directly transmitted bits of the preceding cycle stored in the receiving subsystem storage device.

Claim 18

A communication system as claimed in claim 11 further comprising a plurality of switches for reconfiguring the communication channel to bypass inoperative communication links.

Claim 19

A communication system for communicating over a plurality of links of a multiple link communication channel in which individual bits of a transmitted word are transmitted in parallel over respective communication links comprising: at least one spare link in the communication channel; a plurality of switches for reconfiguring the channel to bypass a failed link by switching communication from the failed link to the spare link; a transmitting subsystem for transmitting data over the communication channel; and a bit storage device for storing bits of a data word being transmitted while remaining bits of the data word are directly transmitted by the transmitting subsystem, such that data words are transmitted across the communication channel in time multiplexed fashion.

Claim 20

A communication system for communicating over a plurality of links of a multiple link communication channel in which individual bits of a transmitted word are transmitted in parallel over respective communication links comprising: at least one spare link in the communication channel; a plurality of switches for reconfiguring the channel to bypass a failed link by switching communication from the failed link to the spare link; a transmitting subsystem for transmitting data over the communication channel; and a bit storage device for storing bits of a data word being transmitted while remaining bits of the data word are directly transmitted by the transmitting subsystem, such that data words are transmitted across the communication channel in time multiplexed fashion.

Claim 21

A communication system for communicating parallel bits of a data word from input bit lines to output bit lines comprising: plural communication links; a transmitting array of switches for mapping the input bit lines to the communication links, the switches being operable to change a mapping between the input bit lines and the communication links; and a receiving array of switches for mapping the output bit lines to the communication links, the switches being operable to change a mapping between the output bit lines and the communication links; wherein, upon failure of a communication link, the switches of the transmitting and receiving arrays are operated to change the mapping between the input bit lines and the communication links and the mapping between the output bit lines and the communication links such that a predetermined input bit line and a predetermined output bit line, not necessarily the input bit line and output bit line previously mapped to the failed communication link, are mapped to a predetermined link failure position.

Claim 22

A communication system for communicating parallel bits of a data word from input bit lines to output bit lines comprising: plural communication links; a transmitting array of switches for mapping the input bit lines to the communication links, the switches being operable to change a mapping between the input bit lines and the communication links; and a receiving array of switches for mapping the output bit lines to the communication links, the switches being operable to change a mapping between the output bit lines and the communication links; wherein, upon failure of a communication link, the switches of the transmitting and receiving arrays are operated to change the mapping between the input bit lines and the communication links and the mapping between the output bit lines and the communication links such that a predetermined input bit line and a predetermined output bit line, not necessarily the input bit line and output bit line previously mapped to the failed communication link, are mapped to a predetermined link failure position.

Claim 23

A communication system as claimed in claim 15 wherein each array of switches comprises plural stages of switches which operate in series to extend the degree to which the mappings can be changed.

Claim 24

A communication system as claimed in claim 15 wherein the communication links include spare links and changing the mappings replaces links with spare links.

Claim 25

A communication system as claimed in claim 15 further comprising a time multiplexer for time multiplexing data intended for a failed link with data over an operating link.

Claim 26

A communication system as claimed in claim 15 wherein a spare link is located at the predetermined failure position.

Claim 27

A communication system as claimed in claim 15 wherein the transmitting array of switches comprises multiplexer circuits.

Claim 28

A communication system as claimed in claim 15 wherein the transmitting array of switches comprises demultiplexer circuits.

Claim 29

A communication system as claimed in claim 15 wherein the receiving array of switches comprises multiplexer circuits.

Claim 30

A communication system as claimed in claim 15 wherein the receiving array of switches comprises demultiplexer circuits.

Claim 31

A communication system for communicating parallel bits of a data word from input bit lines to output bit lines comprising: plural communication links; a transmitting array of switches for connecting the communication links to the input bit lines, the switches allowing for remapping of interconnections between input bit lines and communication links, each link being connectable to each of at least two input bit lines; a receiving array of switches for connecting the communication links to output bit lines, the switches allowing for remapping of interconnections between the communication links and the output bit lines, each link being connectable to each of at least two output bit lines; and a time multiplexer for time multiplexing data intended for a failed link with data over an operating link.

Claim 32

A communication system for communicating parallel bits of a data word from input bit lines to output bit lines comprising: plural communication links; a transmitting array of switches for connecting the communication links to the input bit lines, the switches allowing for remapping of interconnections between input bit lines and communication links, each link being connectable to each of at least two input bit lines; a receiving array of switches for connecting the communication links to output bit lines, the switches allowing for remapping of interconnections between the communication links and the output bit lines, each link being connectable to each of at least two output bit lines; and a time multiplexer for time multiplexing data intended for a failed link with data over an operating link.