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US5438544A
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Non-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the device
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1994-01-28
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Granted: 1995-08-01
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Expires: 2014-01-28
Abstract
Abstract A non-volatile semiconductor memory device includes a control circuit provided for controlling erasure and writing of data with respect to memory cell transistors. In an erase operation, the control circuit generates a voltage which is required for bringing memory cell transistors to an overerased state. In a write operation, the control circuit sets respective voltages of each control gate of memory cell transistors to be an identical one, and generates a first voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to present a first logic level. A second voltage is generated which is required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to present a second logic level. The control circuit further brings all of memory cell transistors included in a minimal block portion which is an object of erasure to an overerased state, by means of a flash erasure. It is therefore possible to realize a high speed erase operation and a high speed write operation.
Inventors
- 👤 Takami Makino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:41
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/10; G11C16/12; G11C16/14; G11C16/16; G11C16/344; G11C16/3445
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
301 words
A non-volatile semiconductor memory device wherein each transistor having a two-layer gate structure with a control gate and a floating gate is constituted as a memory cell transistor, the non-volatile semiconductor memory device comprising: a control circuit provided for controlling erasure and writing of data with respect to memory cell transistors, the control circuit generating, in an erase operation, a voltage required for bringing memory cell transistors to an overerased state, and in a write operation, the control circuit applying an identical voltage to each control gate of a plurality of memory cell transistors connected to an identical word line, and generating a first voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a first logic level, and a second voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a second logic level, one of said generated first voltage and second voltage being supplied to a bit line corresponding to each of the memory cell transistors, the control circuit bringing all of memory cell transistors included in an object block portion of erasure, to an overerased state, by means of a flash erasure, wherein the control circuit controls a write operation with units of a plurality of memory cell transistors in an overerased state connected to an identical word line, the write operation including a first writing into memory cell transistors which should be released from the overerased state to thereby retain data corresponding to the first logic level, and a second writing into memory cell transistors which should be released from the overerased state to thereby retain data corresponding to the second logic level.
Claim 2
Dependent Claim
301 words
A non-volatile semiconductor memory device wherein each transistor having a two-layer gate structure with a control gate and a floating gate is constituted as a memory cell transistor, the non-volatile semiconductor memory device comprising: a control circuit provided for controlling erasure and writing of data with respect to memory cell transistors, the control circuit generating, in an erase operation, a voltage required for bringing memory cell transistors to an overerased state, and in a write operation, the control circuit applying an identical voltage to each control gate of a plurality of memory cell transistors connected to an identical word line, and generating a first voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a first logic level, and a second voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a second logic level, one of said generated first voltage and second voltage being supplied to a bit line corresponding to each of the memory cell transistors, the control circuit bringing all of memory cell transistors included in an object block portion of erasure, to an overerased state, by means of a flash erasure, wherein the control circuit controls a write operation with units of a plurality of memory cell transistors in an overerased state connected to an identical word line, the write operation including a first writing into memory cell transistors which should be released from the overerased state to thereby retain data corresponding to the first logic level, and a second writing into memory cell transistors which should be released from the overerased state to thereby retain data corresponding to the second logic level.
Claim 3
Dependent Claim
28 words
The non-volatile semiconductor memory device as set forth in claim 1, wherein the control circuit controls the first writing and the second writing to be simultaneously carried out.
Claim 4
Dependent Claim
267 words
A non-volatile semiconductor memory device wherein each transistor having a two-layer gate structure with a control gate and a floating gate is constituted as a memory cell transistor, the non-volatile semiconductor memory device comprising: a control circuit provided for controlling erasure and writing of data with respect to memory cell transistors, the control circuit generating, in an erase operation, a voltage required for bringing memory cell transistors to an overerased state, and in a write operation, the control circuit applying an identical voltage to each control gate of a plurality of memory cell transistors connected to an identical word line, and generating a first voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a first logic level, and a second voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a second logic level, one of skid generated first voltage and second voltage being supplied to a bit line corresponding to each of the memory cell transistors; and a verify/monitor circuit block including a verify/monitor memory cell transistor connected to each of a plurality of word lines included in an object block portion of flash erasure, the control circuit reading data of each verify/monitor memory cell transistor to which overerasure of writing is carried out simultaneously with regular memory cell transistors included in said object block portion, and thus judging respective states of erasure or writing of the regular memory cell transistors.
Claim 5
Dependent Claim
267 words
A non-volatile semiconductor memory device wherein each transistor having a two-layer gate structure with a control gate and a floating gate is constituted as a memory cell transistor, the non-volatile semiconductor memory device comprising: a control circuit provided for controlling erasure and writing of data with respect to memory cell transistors, the control circuit generating, in an erase operation, a voltage required for bringing memory cell transistors to an overerased state, and in a write operation, the control circuit applying an identical voltage to each control gate of a plurality of memory cell transistors connected to an identical word line, and generating a first voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a first logic level, and a second voltage required for releasing memory cell transistors in an overerased state from the overerased state to thereby cause the memory cell transistors to retain data corresponding to a second logic level, one of skid generated first voltage and second voltage being supplied to a bit line corresponding to each of the memory cell transistors; and a verify/monitor circuit block including a verify/monitor memory cell transistor connected to each of a plurality of word lines included in an object block portion of flash erasure, the control circuit reading data of each verify/monitor memory cell transistor to which overerasure of writing is carried out simultaneously with regular memory cell transistors included in said object block portion, and thus judging respective states of erasure or writing of the regular memory cell transistors.
Claim 6
Dependent Claim
27 words
The non-volatile semiconductor memory device as set forth in claim 3, wherein the verify/monitor circuit block is provided in a region adjacent to the object block portion.
Claim 7
Dependent Claim
45 words
The non-volatile semiconductor memory device as set forth in claim 4, wherein each verify/monitor memory cell transistor is provided for regular memory cell transistors connected to an identical word line included in said object block portion, and is provided to have an individual bit line.
Claim 8
Independent Claim
141 words
A method of writing data in a non-volatile semiconductor memory device wherein each transistor having a two-layer gate structure with a control gate and a floating gate is constituted as a memory cell transistor, the method comprising the steps of: executing a flash erasure with respect to all of memory cell transistors included in an object block portion of erasure, to thereby bring all of the memory cell transistors to an overerased state; simultaneously writing "0" data or "1" data, with units of a plurality of memory cell transistors connected to an identical word line in the object block of erasure; and judging whether or not memory cell transistors with insufficient writing of "1" data are present among the plurality of memory cell transistors, and where the judging indicates YES, executing the step of simultaneously writing "0" data or "1" data.
Claim 9
Independent Claim
141 words
A method of writing data in a non-volatile semiconductor memory device wherein each transistor having a two-layer gate structure with a control gate and a floating gate is constituted as a memory cell transistor, the method comprising the steps of: executing a flash erasure with respect to all of memory cell transistors included in an object block portion of erasure, to thereby bring all of the memory cell transistors to an overerased state; simultaneously writing "0" data or "1" data, with units of a plurality of memory cell transistors connected to an identical word line in the object block of erasure; and judging whether or not memory cell transistors with insufficient writing of "1" data are present among the plurality of memory cell transistors, and where the judging indicates YES, executing the step of simultaneously writing "0" data or "1" data.
References Cited (Backward Citations)
US5270979A
Cited
US5295107A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-07-31 | 1999-01-30 | 1999-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-31 | 2003-01-30 | 2003-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-31 | 2007-01-30 | 2007-08-01 | $7700.00 | Window Closed / Lapsed |