Abstract A phase difference measuring device includes a phase detector, a low-pass filter/voltage controlled oscillator, a reference signal selector for selecting either an internal reference signal or an external reference signal as a reference signal, a phase comparator for comparing an undertest signal with the selected reference signal and obtaining a phase difference between the two compared signal. The internal reference signal is selected when the undertest signal is a jittering signal, and the external reference signal is selected when the undertest signal is a wandering signal. The undertest signal, the selected reference signal, and a relatively high frequency clock signal from external are sent to the phase comparator and a phase difference between the undertest signal and the selected reference signal is counted by the relatively high frequency clock signal.
A phase difference measuring device comprising a phase detector, a low-pass filter/voltage controlled oscillator, a reference signal selector for selecting either an internal reference signal or an external reference signal, a phase comparator for comparing an undertest signal with the selected reference signal and obtaining a phase difference between the two compared signals; wherein the phase detector together with the low-pass filter/voltage controlled oscillator constitute a phase lock loop for detecting the phase of the undertest signal; the internal reference signal outputted from the low-pass filter/voltage controlled oscillator and the external reference signal are sent to the reference signal selector, and the internal reference signal is selected when the undertest signal is a jittering signal, and the external reference signal is selected when the undertest signal is a wandering signal; the undertest signal and the selected reference signal are sent to the phase comparator for obtaining a phase difference therebetween; an initialization signal for initializing the phase comparator and a relatively high frequency clock signal for counting the phase difference are sent to the phase comparator; a phase difference between the undertest signal and the selected reference signal is counted in the phase comparator and a digital signal representing the phase difference outputted from the phase comparator.
Claim 2
Dependent Claim
207 words
A phase difference measuring device comprising a phase detector, a low-pass filter/voltage controlled oscillator, a reference signal selector for selecting either an internal reference signal or an external reference signal, a phase comparator for comparing an undertest signal with the selected reference signal and obtaining a phase difference between the two compared signals; wherein the phase detector together with the low-pass filter/voltage controlled oscillator constitute a phase lock loop for detecting the phase of the undertest signal; the internal reference signal outputted from the low-pass filter/voltage controlled oscillator and the external reference signal are sent to the reference signal selector, and the internal reference signal is selected when the undertest signal is a jittering signal, and the external reference signal is selected when the undertest signal is a wandering signal; the undertest signal and the selected reference signal are sent to the phase comparator for obtaining a phase difference therebetween; an initialization signal for initializing the phase comparator and a relatively high frequency clock signal for counting the phase difference are sent to the phase comparator; a phase difference between the undertest signal and the selected reference signal is counted in the phase comparator and a digital signal representing the phase difference outputted from the phase comparator.
Claim 3
Dependent Claim
161 words
A phase difference measuring device as claimed in claim 1, wherein the phase comparator comprises a first divider for receiving the undertest signal and outputting a first divided signal in response, a second divider for receiving the selected reference signal and outputting a second divided signal in response, an initialization circuit for receiving the initialization signal and providing a reset signal to the first and the second dividers, an AND gate coupled to receive the relatively high frequency clock signal and output a clock signal in response,.a counter coupled to receive the clock signal and the second divided signal and output a counted signal, a latch coupled to receive the counted signal and output the digital signal representing the phase difference in response to every rising edge of the first divided signal; wherein the second divided signal resets the counter at its falling edge of each cycle and enables the counter to count again at its rising edge of each cycle.