Phase measurement system using a dithered clock

Claim 3

A method for measuring the phase shift as claimed in claim 1, wherein the step of generating a dithered clock signal, comprises the step of adding a dithering signal to a clock signal, wherein the dithering signal has a frequency less than or equal to one half of the frequency of the measured input signal and wherein the averaging of a plurality of measurements is over at least one period of the dithering signal.

Claim 4

A method for measuring the phase shift as claimed in claim 2, wherein the step of adding the dithering signal to the clock signal, comprises the steps of: summing the amplitude of the dithering signal with the amplitude of a DC signal to generate a summed DC signal; generating an output signal that has a frequency that is proportional to the amplitude of the summed DC signal, wherein if the amplitude of the summed DC signal is zero then the frequency of the output signal is approximately N times the frequency of the reference signal, wherein N is a number greater than or equal to two; using the output signal as the dithered clock signal; dividing down part of the output signal by N to produce a divided down signal which has an average frequency which is approximately equal to the frequency of the reference input signal; measuring the phase difference between the reference input signal and the divided down signal; and generating the DC signal, which has an amplitude proportional to the phase difference between the reference input signal and the divided down signal.

Claim 5

A method for measuring the phase shift as claimed in claim 3, wherein the step of measuring the phase difference between the reference input signal and the measured input signal, comprises the steps of: synchronizing the reference input signal with the dithered clock signal to create a synchronized reference signal; and synchronizing the measured input signal with the dithered clock signal to create a synchronized measured signal.

Claim 6

A method for measuring the phase shift as claimed in claim 4, further comprising the steps of: dividing down the synchronized measured signal frequency by M, wherein M is a number greater than or equal to two to generate a signal with a frequency equal to the frequency of the synchronized measured signal frequency divided by M; and using the divided down signal as the dithering signal.

Claim 7

A method for measuring the phase shift as claimed in claim 5, wherein M is a whole number and M measurements of the phase differences between the reference input signal and the measured input signal are averaged together.

Claim 8

A method for measuring the phase shift as claimed in claim 6, wherein the step of measuring the phase difference between the reference input signal and the measured input signal, further comprises the steps of: comparing the synchronized reference signal with the synchronized measured signal and decrementing a major value if only a leading edge of the synchronized reference signal is encountered and incrementing the major value if only a leading edge of the synchronized measured signal is encountered; setting a minor value to N-1 when a leading edge of the synchronized reference signal is encountered; decrementing the minor value by one with each rising edge of the dithered clock signal encountered subsequent to the leading edge of the synchronized reference signal; accumulating a running sum of the major and minor values when a leading edge of the synchronized measured signal is encountered for a full period of the dithering signal.

Claim 9

A method for measuring the phase shift as claimed in claim 7, wherein the step adding the dithering signal to the clock signal, further comprises the step of, filtering the DC signal before it is summed with the amplitude of the dithering signal.

Claim 10

A method for measuring the phase shift as claimed in claim 7, wherein the step adding the dithering signal to the clock signal, further comprises the step of, filtering the summed DC signal.

Claim 11

A method for measuring the phase shift as claimed in claim 9, wherein the step of adding a dithering signal to the clock signal, further comprises the step of converting the dithering signal from a square wave to triangle wave before summing it with the DC signal.

Claim 14

An apparatus for measuring the phase shift as claimed in claim 11, wherein the means for generating a dithered clock signal, comprises; means for generating a dithering signal which has a frequency less than or equal to one half the frequency of the measured input signal, wherein the means for averaging a plurality of measurements averages the measurements over at least one period of the dithering signal; and a phase-locked loop.

Claim 15

An apparatus for measuring the phase shift as claimed in claim 12, wherein the phase-locked loop further comprises; means for adding the dithering signal with a signal from the phase-locked loop; a voltage controlled oscillator which has as input the output from the adding means, and which has an output frequency which is centered on approximately N times the frequency of the reference signal, wherein N is a number greater than or equal to two and wherein the output of the voltage controlled oscillator is the dithered clock signal; a first frequency divider, which uses as input the output of the voltage controlled oscillator, and which divides down the frequency of the signal from the voltage controlled oscillator by N and produces as output a signal which has an average frequency which is approximately equal to the frequency of the reference input signal; and a phase detector, which receives as input the output from the frequency divider and the reference input signal, wherein the phase detector outputs a signal corresponding to the phase difference between the reference input signal and the output of the phase divider, and wherein the output of the phase detector is directed to the adding means as the input signal from the phase-locked loop.

Claim 16

An apparatus for measuring the phase shift as claimed in claim 13, wherein the means for measuring the phase difference comprises: means for synchronizing the reference input signal with the dithered clock signal to create a synchronized reference signal; and means for synchronizing the measured input signal with the dithered clock signal to create a synchronized measured signal.

Claim 17

An apparatus for measuring the phase shift as claimed in claim 14, further comprising: a second frequency divider, which divides down the synchronized measured input frequency by M, wherein M is a number greater than or equal to two, to generate a signal with a frequency equal to the frequency of synchronized measured signal divided by M, which is used as the dithering signal.

Claim 18

An apparatus for measuring the phase shift, as claimed in claim 15, wherein M is a whole number and M measurements of the phase differences between the reference input signal and the measured input signal are averaged together.

Claim 19

An apparatus for measuring the phase shift as claimed in claim 16, wherein the means for measuring the phase difference between the reference input signal and the measured input signal further comprises: an anticoincidence device which receives as input the synchronized measured signal and the synchronized reference signal; a major up down counter which receives as input the output from the anticoincidence device, which produces a value in a register in the major counter; a minor counter, which receives as input the synchronized reference signal wherein the leading edge of the synchronized reference signal causes a register in the minor counter to be set to a value of N-1, and which receives as input the dithered clock signal wherein a rising edge of the dithered clock signal subsequent to the leading edge of the synchronized reference signal causes the value in the register of the minor counter to be decremented by one. a counter latch which receives the value in the register of the minor counter as input and and the value in the register of the major counter as input, and stores these values, and which receives the synchronized measured signal as input wherein a leading edge of the synchronized measured signal causes the counter latch to release the stored values as output; and an adder, which receives the output from the counter latch as input, and which accumulates the output from the counter latch for a full period of the dithering signal.

Claim 20

An apparatus for measuring the phase shift as claimed in claim 17, wherein the phase-locked loop further comprises a low pass filter which filters the output signal from the phase detector before the signal reaches the adding means.

Claim 21

An apparatus for measuring the phase shift as claimed in claim 17, wherein the phase-locked loop further comprises a low pass filter which filters the output of the adding means before the signal reaches the voltage controlled oscillator.

Claim 22

An apparatus for measuring the phase shift as claimed in claim 19, wherein the means for generating a dithering signal further comprises a square wave to triangle wave circuit which receives as input the signal from the second frequency divider, and wherein the output is sent to the adding means in the phase-locked loop.