US5437017A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system
Assignee: International Business Machines Corp
•
Filing: 1992-10-09
•
Granted: 1995-07-25
•
Expires: 2012-10-09
Abstract
Abstract Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor. Thus, a broadcast translation lookaside buffer invalidate (TLBI) instruction may only be executed by the other processors within a multiprocessor system if it has been accepted by all processors within the system. After initiating execution of a translation lookaside buffer invalidate (TLBI) instruction at all processors within the system, the execution of pending instructions is temporarily terminated until after the translation lookaside buffer invalidate (TLBI) instruction has been executed. Thereafter, the execution of instructions is suspended until all read and write operations within the memory queue have achieved coherency. Next, all suspended and/or prefetched instructions are refetched utilizing the modified translation lookaside buffer (TLB) to ensure that the address utilized is still valid.
Inventors
- 👤 Charles R. Moore
- 👤 John S. Muhich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:28
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F2212/00; G06F2212/68; G06F2212/682
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
215 words
A method for maintaining translation lookaside buffer coherency in a multiprocessor computer system having system memory and a plurality of processors coupled together via a bus, each of said plurality of processors including multiple processor units for executing multiple instructions, a memory management unit for performing read and write operations within said system memory and an associated translation lookaside buffer for translating effective addresses into real memory addresses within said system memory, said method comprising the steps of: broadcasting a translation lookaside buffer invalidate bus structure along said bus in response to an execution of an associated translation lookaside buffer invalidate instruction within a selected one of said plurality of processors; accepting said translation lookaside buffer invalidate bus structure at any remaining one of said plurality of processors only in response to an absence of a pending execution of a translation lookaside buffer invalidate instruction therein; broadcasting a retry message along said bus in response to a nonacceptance of said translation lookaside buffer invalidate bus structure at any one of said plurality of processors; and executing said associated translation lookaside buffer invalidate instruction at all remaining processors among said plurality of processors only in response to an acceptance of said translation lookaside buffer invalidate bus structure at all remaining processors among said plurality of processors.
Claim 2
Independent Claim
215 words
A method for maintaining translation lookaside buffer coherency in a multiprocessor computer system having system memory and a plurality of processors coupled together via a bus, each of said plurality of processors including multiple processor units for executing multiple instructions, a memory management unit for performing read and write operations within said system memory and an associated translation lookaside buffer for translating effective addresses into real memory addresses within said system memory, said method comprising the steps of: broadcasting a translation lookaside buffer invalidate bus structure along said bus in response to an execution of an associated translation lookaside buffer invalidate instruction within a selected one of said plurality of processors; accepting said translation lookaside buffer invalidate bus structure at any remaining one of said plurality of processors only in response to an absence of a pending execution of a translation lookaside buffer invalidate instruction therein; broadcasting a retry message along said bus in response to a nonacceptance of said translation lookaside buffer invalidate bus structure at any one of said plurality of processors; and executing said associated translation lookaside buffer invalidate instruction at all remaining processors among said plurality of processors only in response to an acceptance of said translation lookaside buffer invalidate bus structure at all remaining processors among said plurality of processors.
Claim 3
Dependent Claim
47 words
The method for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 1, further including the step of terminating execution of pending instructions within each of said plurality of processors in response to pending execution of said associated translation lookaside buffer invalidate instruction.
Claim 4
Dependent Claim
42 words
The method for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 2, further including the step of temporarily storing addresses of said pending instructions in response to pending execution of said associated translation lookaside buffer invalidate instruction.
Claim 5
Dependent Claim
49 words
The method for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 3, further including the step of inserting said associated translation lookaside buffer invalidate instruction into a processor unit within each of said plurality of processors following termination of pending execution of instructions therein.
Claim 6
Dependent Claim
53 words
The method for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 4, further including the step of suspending execution of instructions within each of said plurality of processors until such time as coherency is achieved with respect to all pending read and write operations within said system memory.
Claim 7
Dependent Claim
51 words
The method for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 5, further including the step of purging all instructions within each of said plurality of processors in response to achievement of coherency with respect to all pending read and write operations within said system memory.
Claim 8
Dependent Claim
65 words
The method for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 6, further including the step of loading said pending instructions into each of said plurality of processors utilizing said temporarily stored addresses as translated by said translation lookaside buffer after execution of said associated translation lookaside buffer invalidate instruction following purging of all instructions within each of said processors.
Claim 9
Independent Claim
220 words
A system for maintaining translation lookaside buffer coherency in a multiprocessor computer system having system memory and a plurality of processors coupled together via a bus, each of said plurality of processors including multiple processor units for executing multiple instructions, a memory management unit for performing read and write operations within said system memory and an associated translation lookaside buffer for translating effective addresses into real memory addresses within said system memory, said system comprising: means for broadcasting a translation lookaside buffer invalidate bus structure along said bus in response to an execution of an associated translation lookaside buffer invalidate instruction within a selected one of said plurality of processors; means for accepting said translation lookaside buffer invalidate bus structure at any remaining one of said plurality of processors only in response to an absence of a pending execution of a translation lookaside buffer invalidate instruction therein; means for broadcasting a retry message along said bus in response to a nonacceptance of said translation lookaside buffer invalidate bus structure at any one of said plurality of processors; and means for executing said associated translation lookaside buffer invalidate instruction at all remaining processors among said plurality of processors only in response to an acceptance of said translation lookaside buffer invalidate bus structure at all remaining processors among said plurality of processors.
Claim 10
Independent Claim
220 words
A system for maintaining translation lookaside buffer coherency in a multiprocessor computer system having system memory and a plurality of processors coupled together via a bus, each of said plurality of processors including multiple processor units for executing multiple instructions, a memory management unit for performing read and write operations within said system memory and an associated translation lookaside buffer for translating effective addresses into real memory addresses within said system memory, said system comprising: means for broadcasting a translation lookaside buffer invalidate bus structure along said bus in response to an execution of an associated translation lookaside buffer invalidate instruction within a selected one of said plurality of processors; means for accepting said translation lookaside buffer invalidate bus structure at any remaining one of said plurality of processors only in response to an absence of a pending execution of a translation lookaside buffer invalidate instruction therein; means for broadcasting a retry message along said bus in response to a nonacceptance of said translation lookaside buffer invalidate bus structure at any one of said plurality of processors; and means for executing said associated translation lookaside buffer invalidate instruction at all remaining processors among said plurality of processors only in response to an acceptance of said translation lookaside buffer invalidate bus structure at all remaining processors among said plurality of processors.
Claim 11
Dependent Claim
46 words
The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 8, further including means for terminating execution of pending instructions within each of said plurality of processors in response to pending execution of said associated translation lookaside buffer invalidate instruction.
Claim 12
Dependent Claim
40 words
The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 9, further including means for storing addresses of said pending instructions in response to pending execution of said associated translation lookaside buffer invalidate instruction.
Claim 13
Dependent Claim
48 words
The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 10, further including means for inserting said associated translation lookaside buffer invalidate instruction into a processor unit within each of said plurality of processors following termination of pending execution of instructions therein.
Claim 14
Dependent Claim
53 words
The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 11, further including means for suspending execution of instructions within each of said plurality of processors until such time as coherency is achieved with respect to all in pending read and write operations within said system memory.
Claim 15
Dependent Claim
50 words
The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 12, further including means for purging all instructions within each of said plurality of processors in response to achievement of coherency with respect to all pending read and write operations within said system memory.
Claim 16
Dependent Claim
64 words
The system for maintaining translation lookaside buffer coherency in a multiprocessor computer system according to claim 13, further including means for loading said pending instructions into each of said plurality of processors utilizing said temporarily stored addresses as translated by said translation lookaside buffer after execution of said associated translation lookaside buffer invalidate instruction following purging of all instructions within each of said processors.
References Cited (Backward Citations)
US4733348A
Cited
US5283886A
Cited
US5113514A
Cited
US5197139A
Cited
US5297269A
Cited
US5333296A
Cited
US5303362A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-24 | 1999-01-23 | 1999-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-24 | 2003-01-23 | 2003-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-24 | 2007-01-23 | 2007-07-25 | $7700.00 | Window Closed / Lapsed |