Method and structure for suppressing stress-induced defects in integrated circuit conductive lines

Abstract

Abstract A method for reducing defects in an integrated circuit conductive lines characterized by the steps of providing a conductive line and contacting the conductive line with a layer which reduces stress in the line. There are several mechanisms by which the layer can accomplish the desired stress reduction. One method provides a resilient passivation layer over the conductive line and another method provides a resilient layer beneath the line. Yet another method creates a thin, flexible oxide layer over the conductive line. An extension of this latter method provides a resilient buffer layer over the thin oxide layer and a thick oxide layer over the resilient layer. Another form of stress-reducing layer includes an anti-diffusion layer which reduces the diffusion of metal atoms of the conductive layer into the surrounding oxide. A conductive line structure of the present invention includes at least one conductive line and at least one layer contacting the conductive line which reduces stress in the line. The layer can comprise a resilient layer formed over or beneath the conductive line, or it can include a thin oxide layer disposed over the line. Optionally, the thin oxide layer can be covered with a resilient layer and a thick oxide layer. The layer can also comprise an anti-diffusion layer to reduce diffusion-induced stresses in the conductive line.

Inventors

• 👤 Vivek Jain
• 👤 Dipankar Pramanik

Bibliographic Details