Central processing unit using dual basic processing units and combined result bus

Claim 1

A central processor adapted to selectively perform double precision data manipulation operations single and comprising: A) first and second basic processing units; B) first and second cache units; C) each of said first and second basic processing units including: 1) data manipulation logic circuitry adapted to receive data from said cache units, to perform data manipulations thereon and to issue the data result of such manipulations; 2) a data buffer register for receiving the data result from said data manipulation logic circuitry, said buffer register being divided into upper and lower sections temporarily storing, respectively, upper and lower half-bytes of the data result; and 3) a parity buffer register for receiving a complete set of parity bits in the data result; D) each of said first and second cache units including: 1) bit-by-bit comparison means adapted to receive first and second data words which should be identical and to issue a validating signal if the first and second data words are identical; and 2) storage means; E) first and second upper-half busses; 1) said first upper-half bus coupling said upper section of said data buffer register of said first basic processing unit to said bit-by-bit comparison means of said first cache unit for inputting the first data word input thereto during single precision operations; and 2) said second upper-half bus coupling said upper section of said data buffer register of said second basic processing unit to said bit-by-bit comparison means of said first cache unit for inputting the second data word input thereto during single precision operation; F) first and second lower half busses; 1) said first lower-half bus coupling said lower section of said data buffer register of said first basic processing unit to said bit-by-bit comparison means of said second cache unit for inputting the first data word input thereto during single precision operations; and 2) said second lower-half bus coupling said lower section of said data buffer register of said second basic processing unit to said bit-by-bit comparison means of said cache unit for inputting the second data word input thereto during single precision operations; G) first and second parity busses; 1) said first parity bus coupling said parity buffer of said first basic processing to one of said bit-by-bit comparison means for inputting the first data word input thereto during double precision operations; and 2) said second parity bus coupling said parity buffer to said second basic processing unit to said one of said bit-by-bit comparison means for inputting the second data word input thereto during double precision operations; H) first transfer means responsive to the issuance of one said validating signals to transfer data on said first and second upper-half busses to said storage means of said first cache unit; and I) second transfer means responsive to the issuance of one of said validating signals to transfer data on said first and second lower-half busses to said storage means of said second cache unit.