Method and apparatus for avoiding processor deadly embrace in a multiprocessor system

Claim 1

A multiprocessor system comprising a system memory, a number of system processors and a number of peer processors, each processor being tightly coupled according to a first protocol and a system memory, each of said peer processors comprising; a microprocessor; an on-board local memory; a synchronous local bus connected for tightly coupling said microprocessor and said local memory together to operate according to a second protocol; and, bus interface circuits coupled to said system bus and to said local bus, said bus interface circuits including: first transfer means coupled to said system bus and to said synchronous bus for transferring requests of said each of said peer processors received from any one of said system processors and other ones of said peer processors; second transfer means coupled to said system bus and to said synchronous local bus for transferring requests generated by said microprocessor to said system bus according to said second protocol for reading and writing said system memory or said local memory of another one of said peer processors; system bus response means coupled to said system bus for generating responses to requests transmitted to or received from said system bus, said response means including on-board memory lock indicator means coupled to said system bus; and, processor system lock indicator means coupled to said system bus, to said second transfer means and to said system bus response means; said on-board memory lock indicator being set in response to each memory read lock command generated by one of said processors and received from said system bus which is used for performing a read-modify-write operation on an item of information stored in said local memory in response to each memory read lock command, said first transfer means generating an output signal on said local bus to said microprocessor for inhibiting further accesses by said microprocessor to said local memory until completion of said read-modify-write operation by said local memory; and, said processor lock indicator means being set in response to a first microprocessor memory read lock request transferred to said system bus by said second transfer means and acknowledged by said system bus response means of a specified one of said peer processors, said processor indicator means when set generating an output lock signal for inhibiting said second transfer means from transferring any further microprocessor memory read lock requests to said system bus until completion of said first read lock request thereby preventing a possibility of a deadlock condition in accessing said on-board local memories of said peer processors.