Highly parallel discrete cosine transform engine

Claim 3

The apparatus of claim 1 wherein the input accumulators and the plurality of multiplication circuits are coupled via a transform coefficient bus.

Claim 4

The apparatus of claim 2 wherein the transform coefficient bus includes a plurality of buses, the plurality of buses being cross coupled so that transform coefficients from any accumulator circuit may be received by any multiplication circuit.

Claim 5

The apparatus of claim 1 wherein the multiplication circuits and the output accumulators are coupled via a product bus.

Claim 6

The apparatus of claim 4 wherein the product bus includes a plurality of product buses, the plurality of product buses being cross coupled so that transform products from any multiplication circuit may be received by any output accumulator circuit.

Claim 7

The apparatus of claim 1 wherein the plurality of output accumulators correspond to the row and column locations of the transformed matrix, and each output accumulator provides output data for an individual location of the transformed matrix of data elements.

Claim 8

The apparatus of claim 1 wherein the discrete cosine transform uses a discrete plurality of constants, the plurality of multiplication circuits correspond to the discrete plurality of constants, and each multiplication circuit multiplies the plurality of transform coefficients by one of the discrete plurality of constants.

Claim 11

The apparatus of claim 8 wherein the input accumulators are coupled via an input/output bus.

Claim 12

The apparatus of claim 9 wherein the discrete cosine transform uses a discrete plurality of constants, the means for multiplying includes a computer processor coupled to the input output bus, the computer processor multiplying the plurality of transform coefficients by the discrete plurality of constants to provide the plurality of transform products.

Claim 13

The apparatus of claim 10 wherein the means for output accumulation includes the computer processor, the computer processor accumulating the plurality of transform products to provide the transformed matrix of data elements.

Claim 14

The apparatus of claim 9 wherein the means for output accumulation includes a plurality of output accumulators corresponding to the row and column locations of the transformed matrix, and each output accumulator provides output data element for an individual location of the transformed matrix of data elements.

Claim 15

The apparatus of claim 9 wherein the discrete cosine transform uses a discrete plurality of constants, the means for multiplying includes a plurality of multiplication circuits corresponding to the discrete plurality of constants, and each multiplication circuit multiplies the plurality of transform coefficients by one of the discrete plurality of constants.

Claim 16

A peripheral apparatus for accelerating arithmetic operations of a processor on a first matrix of first data elements to provide a second matrix of second data elements, the first and second matrices each having a plurality of row locations and a plurality of column locations, each data element of the first matrix of data elements having a first address corresponding thereto and each data element of the second matrix of data elements having a second address corresponding thereto, the apparatus comprising a bus having a data portion for transmitting the data elements and an address portion for transmitting addresses from the processor; and a plurality of accumulators coupled to the bus and arranged in a matrix corresponding to the first and second matrices of data elements, each of the plurality of accumulators including an arithmetic unit for performing arithmetic operations on the first data elements to provide second data elements, the arithmetic unit being coupled to the data portion of the bus; and an address selection unit for monitoring the bus for particular first addresses, causing the arithmetic unit to perform arithmetic operations on the first data elements corresponding to the particular first addresses in accordance with programmed rules that are determined by the particular first addresses and causing the arithmetic unit to provide the second data elements corresponding to particular second addresses to the data portion of the bus, the address selection unit being coupled to the address portion of the bus and to the arithmetic unit.

Claim 17

A peripheral apparatus for accelerating arithmetic operations of a processor on a first matrix of first data elements to provide a second matrix of second data elements, the first and second matrices each having a plurality of row locations and a plurality of column locations, each data element of the first matrix of data elements having a first address corresponding thereto and each data element of the second matrix of data elements having a second address corresponding thereto, the apparatus comprising a bus having a data portion for transmitting the data elements and an address portion for transmitting addresses from the processor; and a plurality of accumulators coupled to the bus and arranged in a matrix corresponding to the first and second matrices of data elements, each of the plurality of accumulators including an arithmetic unit for performing arithmetic operations on the first data elements to provide second data elements, the arithmetic unit being coupled to the data portion of the bus; and an address selection unit for monitoring the bus for particular first addresses, causing the arithmetic unit to perform arithmetic operations on the first data elements corresponding to the particular first addresses in accordance with programmed rules that are determined by the particular first addresses and causing the arithmetic unit to provide the second data elements corresponding to particular second addresses to the data portion of the bus, the address selection unit being coupled to the address portion of the bus and to the arithmetic unit.

Claim 18

The apparatus of claim 14 wherein the arithmetic unit performs additions and subtractions in accordance with the programmed rules.

Claim 19

The apparatus of claim 14 wherein the arithmetic operations are performed to provide a discrete cosine transform.

Claim 20

The apparatus of claim 16 wherein the second matrix of data elements correspond to transform coefficients for use in performing a discrete cosine transform.