Patent US4034788A successfully refreshed from Google Patents.
Patent US5434091A successfully refreshed from Google Patents.
US5434091A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making collector up bipolar transistors having reducing junction capacitance and increasing current gain
Assignee: Texas Instruments Inc
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Filing: 1994-10-07
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Granted: 1995-07-18
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Expires: 2014-10-07
Abstract
Abstract This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.
Inventors
- 👤 Darrell Hill
- 👤 Shou-Kong Fan
- 👤 Ali Khatibzadeh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:00
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/00; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011; Y10S148/051; Y10S148/072
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
93 words
A method of fabricating a bipolar transistor, comprising the steps of: a. providing a material structure comprising: a substrate; an emitter contact layer over said substrate; an emitter layer over said emitter contact layer; a base layer over said emitter layer; a collector layer over said base layer; b. removing a portion of said collector, base, and emitter layers to expose an edge of said emitter layer; and c. removing said emitter layer from between said base and emitter contact layer to form an undercut region beneath an edge of said base layer.
Claim 2
Independent Claim
93 words
A method of fabricating a bipolar transistor, comprising the steps of: a. providing a material structure comprising: a substrate; an emitter contact layer over said substrate; an emitter layer over said emitter contact layer; a base layer over said emitter layer; a collector layer over said base layer; b. removing a portion of said collector, base, and emitter layers to expose an edge of said emitter layer; and c. removing said emitter layer from between said base and emitter contact layer to form an undercut region beneath an edge of said base layer.
Claim 3
Dependent Claim
15 words
A method of claim 1, wherein said emitter layer is composed of AlGaAs and GaAs.
Claim 4
Dependent Claim
26 words
The method of claim 1, further comprising the step of forming a base contact on a portion of said base layer lying over said undercut region.
Claim 5
Dependent Claim
29 words
The method of claim 1, further comprising the step of forming said base and emitter contact layers of a first material and said emitter layer of a second material.
Claim 6
Dependent Claim
17 words
The method of claim 4, wherein said first material is GaAs and said second material is AlGaAs.
Claim 7
Dependent Claim
48 words
The method of claim 1, wherein said base layer, said collector layer, and said emitter layer are composed of silicon, and wherein said method includes the further step of doping said base and emitter contact layers a first conductivity, type and said emitter layer a second conductivity type.
Claim 8
Independent Claim
123 words
A method of fabricating a bipolar transistor, comprising the steps of: a. providing a material structure comprising: a substrate; an emitter contact layer over said substrate; an emitter layer over said emitter contact layer; a base layer over said emitter layer; a collector layer over said base layer; b. forming a collector mesa by removing an upper portion of said collector layer; c. doping a lower portion of said collector layer lying over said base layer; d. removing portions of said lower portion, said base layer, and said emitter layers to expose an edge of said emitter layer; e. removing said emitter layer from between said base and emitter contact layers to form an undercut region beneath an edge of said base layer.
Claim 9
Independent Claim
123 words
A method of fabricating a bipolar transistor, comprising the steps of: a. providing a material structure comprising: a substrate; an emitter contact layer over said substrate; an emitter layer over said emitter contact layer; a base layer over said emitter layer; a collector layer over said base layer; b. forming a collector mesa by removing an upper portion of said collector layer; c. doping a lower portion of said collector layer lying over said base layer; d. removing portions of said lower portion, said base layer, and said emitter layers to expose an edge of said emitter layer; e. removing said emitter layer from between said base and emitter contact layers to form an undercut region beneath an edge of said base layer.
Claim 10
Dependent Claim
32 words
The method of claim 7, wherein said step of doping said lower portion of said collector layer includes doping said lower portion to be the same conductivity type as said base layer.
Claim 11
Dependent Claim
22 words
The method of claim 8, further comprising the step of forming a base contact on said lower portion of said collector layer.
Claim 12
Dependent Claim
29 words
The method of claim 7, further comprising the step of forming said base and emitter contact layers of a first material and said emitter layer of a second material.
Claim 13
Dependent Claim
47 words
The device of claim 7, wherein said base layer, said emitter layer, and said collector layer are composed of silicon, and said method includes the further step of doping said base and emitter contact layers a first conductivity type and said emitter layer a second conductivity type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |