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US5433822A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing semiconductor device with copper core bumps

Assignee: Amkor Technology Singapore Holding Pte Ltd
•
Filing: 1992-12-22
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Granted: 1995-07-18
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Expires: 2012-12-22
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Abstract

Abstract A semiconductor device has circuit patterns formed on upper and lower surfaces of a laminated board with both surfaces lined with copper and interconnected by through holes, an IC chip mounted on the upper pattern, and external connection terminals mounted on the lower pattern, the external connection terminals comprising copper core bumps. According to a method of manufacturing such a semiconductor device, the same etching process as pattern etching for forming the circuit pattern are effected in bump forming regions on the circuit pattern formed by the resist pattern.

Inventors

  • 👤 Seiichi Mimura
  • 👤 Junichiro Shimizu
  • 👤 Takayuki Tajiri
  • 👤 Shingo Ichikawa
  • 👤 Hiroyuki Kaneko
  • 👤 Masayuki Ohi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 23:22
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/40; H05K3/4007; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W90/00; H10W90/701; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0347; H05K2201/0364; H05K2201/0367; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09481; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/14; H05K2203/1476; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3436; H05K3/42; H05K3/423; H05K3/425; H05K3/427; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/851; H10W72/874; H10W72/884; H10W90/731; H10W90/734; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 62 words
A method of manufacturing a semiconductor device by forming copper core bumps on a circuit pattern on a circuit board by way of plating using a resist pattern, characterized by forming a solvent-reactive first dry film and a water-soluble second dry film as successive layers as said resist pattern, and removing said second dry film after the copper core bumps are formed.
Claim 2
Independent Claim 62 words
A method of manufacturing a semiconductor device by forming copper core bumps on a circuit pattern on a circuit board by way of plating using a resist pattern, characterized by forming a solvent-reactive first dry film and a water-soluble second dry film as successive layers as said resist pattern, and removing said second dry film after the copper core bumps are formed.
Claim 3
Independent Claim 234 words
A method of manufacturing a circuit board for a semiconductor device, comprising: a through hole forming step for forming through holes in a circuit board with thin copper foils on both surfaces of the circuit board, a plating step for forming copper plates on the surfaces of the circuit board with the through holes, a patterning step for forming, by using an etching solution, a die pattern region on one surface of the circuit board and bump forming regions on the other surface of the circuit board, a resist/dry film laminating step for laminating resist/dry films on both surfaces of the circuit board after patterning step to thereby form resist pattern openings at the die pattern region and the bump forming regions, said resist/dry film laminating step including radiation and development, an activation etching step for removing residues of the resist/dry films dissolved by the radiation and development in the resist/dry film laminating step and deposited on the bump forming regions to thereby activate a surface of copper at the bump forming regions, a mask/dry film laminating step for laminating a mask/dry film on the resist/dry film at a side of the die pattern region to thereby mask the die pattern region, a bump forming step for forming copper core bumps on the bump forming regions on the board, and a mask/dry film developing step for removing the mask/dry film on the resist/dry film.
Claim 4
Independent Claim 234 words
A method of manufacturing a circuit board for a semiconductor device, comprising: a through hole forming step for forming through holes in a circuit board with thin copper foils on both surfaces of the circuit board, a plating step for forming copper plates on the surfaces of the circuit board with the through holes, a patterning step for forming, by using an etching solution, a die pattern region on one surface of the circuit board and bump forming regions on the other surface of the circuit board, a resist/dry film laminating step for laminating resist/dry films on both surfaces of the circuit board after patterning step to thereby form resist pattern openings at the die pattern region and the bump forming regions, said resist/dry film laminating step including radiation and development, an activation etching step for removing residues of the resist/dry films dissolved by the radiation and development in the resist/dry film laminating step and deposited on the bump forming regions to thereby activate a surface of copper at the bump forming regions, a mask/dry film laminating step for laminating a mask/dry film on the resist/dry film at a side of the die pattern region to thereby mask the die pattern region, a bump forming step for forming copper core bumps on the bump forming regions on the board, and a mask/dry film developing step for removing the mask/dry film on the resist/dry film.
Claim 5
Dependent Claim 36 words
A method of manufacturing a circuit board according to claim 2, wherein removal of residues of the resist/dry films in the activation etching step is made by using the etching solution used in the patterning step.
Claim 6
Dependent Claim 31 words
A method of manufacturing a circuit board according to claim 3, wherein the removal of the residues of the resist/dry film in the activation etching step is performed for 5-30 seconds.
Claim 7
Dependent Claim 40 words
A method of manufacturing a circuit board according to claim 4, wherein said patterning step includes laminating mask dry films, exposing and developing the mask dry films, and etching the copper plates on the circuit board by the etching solution.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-07-17 1999-01-16 1999-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-07-17 2003-01-16 2003-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-07-17 2007-01-16 2007-07-18 $7700.00 Window Closed / Lapsed

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