Equalizing method and apparatus

Claim 1

An equalizing apparatus for equalizing received digital transmission signals, said transmission signals comprising a reception slot which includes a sync word and a data slot, said apparatus comprising: an input buffer for transiently storing at least the sync word of the current reception slot, the data in the data slot of a current reception slot and the sync word of the subsequent reception slot; an equalizer for equalizing the reception slot supplied thereto; a processing circuit for calculating equalization characteristics of said equalizer and for changing the equalization characteristics of said equalizer; an equalized state detection means for outputting signals corresponding to an equalized state of a current reception slot; an output buffer for transiently storing an output of said equalizer; a control circuit for detecting an error site in a current reception slot based on output signals from said equalized state detection means and for controlling the input buffer and the output buffer, said control circuit including a data generating means for generating a sync word based on prior sync word data and a data discriminator circuit for adjudicating whether arbitrary data in the current data slot is correct data; a changeover switch responsive to said control circuit for transmitting to said processing circuit the prior sync word data from said data generating means when said sync word is being equalized by said equalizer, and for transmitting to said processing circuit the arbitrary data found to be correct by said data discrimination circuit when the arbitrary data in said data slot has been equalized by said equalizer, and wherein said equalized state detection means includes a subtractor for generating a difference signal indicative of the difference between the output of the equalizer and an output of said changeover switches; and said control circuit is operable to detect an error site within a reception slot when the square of the absolute value of the difference signal exceeds a predetermined value; wherein said control circuit is operable to discontinue forward equalization starting from the sync word of the current reception slot by said equalizer on detection of said error site, and to initialize using the sync word of the reception slot subsequent and adjacent to the current reception slot from said input buffer, and thereafter perform reverse equalization starting from the trailing end of the sync word of the reception slot subsequent and adjacent to the current reception slot.